
Programmers Model
ARM DDI 0503F Copyright © 2012-2013 ARM. All rights reserved. 3-39
ID062813 Non-Confidential
Test chip SCC Register 43
The CFGREG43 Register characteristics are:
Purpose Configuration register 0 that enables you to read and write Cortex-A7
cluster configuration settings.
Usage constraints There are no usage constraints.
Configurations Not applicable.
Attributes See Table 3-6 on page 3-13.
Figure 3-21 shows the bit assignments.
Figure 3-21 Test chip CFGREG43 Register bit assignments
[5:4] CP15SDISABLE[1:0] Disables write to secure Cortex-A15 core registers:
b0
Enable write to secure Cortex-A15 core registers.
b1
Disable write to secure Cortex-A15 core registers.
The default is
b00
.
[3:2] - Reserved. Do not modify.
[1:0] CFGEND[1:0] Maps to the CFGEND[1:0] bus. Configures cores as bigend:
b0
Configures cores as little-end.
b1
Configures cores as big-end.
The default is
b00
.
Table 3-22 Test chip CFGREG42 Register bit assignments (continued)
Bits Name Function
31 16 15 8 0
110111 0 0000000000010 0111 000000
7
01
Reserved
SPIDEN[2:0]
30 28 27 26 24 23 22 20 19 18 14 12 11 10 43
Reserved
Reserved
Reserved
Reserved
Reserved
NIDEN[2:0]
DBGEN[2:0]
CFGTE[2:0]
VINITHI_CORE[2:0]
CLUSTER_ID
CFGEND[2:0]
Reserved
Komentáře k této Příručce