ARM AMBA NIC-301 Specifikace stáhnout pdf (Strana 163)

HDLCD controller

ID062813 Non-Confidential

Table B-6 shows the bit assignments.

Frame Buffer Base Address Register

The FB_BASE Register characteristics are:

Purpose Holds the address of the first pixel of the first line in the frame buffer.

Usage constraints There are no usage constraints.

Configurations Available in all HDLCD controller configurations.

Attributes See Table B-1 on page B-3.

Figure B-6 shows the bit assignments.

Figure B-6 Frame Buffer Base Address Register bit assignments

Table B-7 shows the bit assignments.

Frame Buffer Line Length Register

The FB_LINE_LENGTH Register characteristics are:

Purpose Holds the length of each frame buffer line in bytes.

Table B-6 Interrupt Status Register bit assignments

Bits Name Function

[31:4] - Reserved, read undefined.

[3] UNDERRUN No data was available to display while DATAEN was active.

This interrupt triggers if the controller does not have pixel data available to drive when

DATAEN is active. When this occurs, the controller drives the default color for the rest of the

screen and attempts to display the next frame correctly.

[2] VSYNC Vertical sync is active.

This interrupt triggers at the moment the VSYNC output goes active.

[1] BUS_ERROR The DMA module received a bus error while reading data.

This interrupt triggers if any frame buffer read operation ever reports an error.

[0] DMA_END The DMA module has finished reading a frame.

This interrupt triggers when the last piece of data for a frame has been read. The DMA

immediately continues on the next frame, so this interrupt only ensures that the frame buffer for

the previous frame is no longer required.

31 302

FB_BASE_ADDR

Reserved

Table B-7 Frame Buffer Base Address Register bit assignments

Bits Name Function

[31:3] FB_BASE_ADDR Frame buffer base address

[2:0] - Reserved, write as zero, read undefined

1 2 ... 158 159 160 161 162 163 164 165 166 167 168 ... 177 178

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ARM AMBA NIC-301 Specifikace Strana 163