
Programmers Model
ARM DDI 0503F Copyright © 2012-2013 ARM. All rights reserved. 3-59
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3.4.10 Static memory controller, PL354
The PL354 Static Memory Controller (SMC) connects between the NIC-AXI interconnect and
the PL220 interface that drives the SMB.
SMC organization
The SMC accesses these devices on the motherboard using the following chip selects:
CS0 NOR flash 0.
CS1 PSRAM.
CS2 Video, ETH, USB.
CS3 System registers and peripherals.
CS4 NOR flash 1.
CS5 Reserved.
CS6 Reserved.
CS7 Reserved.
Static memory controller implementation
Table 3-39 provides information on the static memory controller implementation.
ECC FALSE
Release version ARM DMC-400 r0p0
Reference documentation
CoreLink
™
DDR2 DMC-400 Dynamic Memory
Controller Technical Reference Manual
Table 3-38 DDR2 memory controllers implementation (continued)
Property Value
Table 3-39 Static memory controller implementation
Property Value
Memory base address
0x00_7FFD_0000
Interrupts 118,119
AXI width 64
MEMIF width 32
MEMIF CS 8
Exclusion monitors 2
CFIFO depth 8
WFIFO depth 16
RFIFO depth 16
AID width 15
ECC FALSE
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