ARM AMBA NIC-301 Specifikace stáhnout pdf (Strana 34)

Hardware Description

ID062813 Non-Confidential

Test chip SCC Register 6 on page 3-22 controls the internal resets. The fine-grained resets select

specific cores or other blocks according to the bits you select in this register.

Each cluster contains the following power domains:

VCORE Contains most of the cluster logic including all the cores.

VSOC Contains the interface logic between the clusters and the rest of the test chip.

The reset signals operate as follows:

A7_NVCORERESET

Resets all of the A7 VCORE domain and overrides all the fine-grained A7 resets.

A15_NVCORERESET

Resets all of the A15 VCORE domain and overrides all the fine-grained A15

resets.

A7_NVCORERESET - Yes Yes Yes Yes Yes Yes A7_CLK

domain.

Overrides

fine-grain

resets.

This reset

selects all

cores in the

cluster. It

does not

select

specific

cores.

A15_NVSOCRESET No No No No No No No ACLK and

PCLK

domain.

A15_NVCORERESET - Yes Yes Yes Yes Yes Yes A15_CLK

domain.

Overrides

fine-grain

resets.

This reset

selects all

cores in the

cluster. It

does not

select

specific

cores.

Table 2-2 Internal resets controlled by SCC registers (continued)

Reset Core

NEON

and

VFP

Debug

PTM

ETM

Breakpoint

and

watchpoint

logic

Shared

debug,

APB, CTI

and CTM

logic

Shared L2

memory

system,

GIC and

timer

logic

Comment

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