ARM AMBA NIC-301 Specifikace stáhnout pdf (Strana 161)

HDLCD controller

ID062813 Non-Confidential

Interrupt Mask Register

The INT_MASK Register characteristics are:

Purpose Holds the bit mask that enables an interrupt source if the corresponding

mask bit is set to 1.

Usage constraints There are no usage constraints.

Configurations Available in all HDLCD controller configurations.

Attributes See Table B-1 on page B-3.

Figure B-4 shows the bit assignments.

Figure B-4 Interrupt Mask Register bit assignments

Table B-5 shows the bit assignments.

[2] VSYNC Vertical sync is active.

This interrupt triggers at the moment the VSYNC output goes active.

[1] BUS_ERROR The DMA module received a bus error while reading data.

This interrupt triggers if any frame buffer read operation ever reports an error.

[0] DMA_END The DMA module has finished reading a frame.

This interrupt triggers when the last piece of data for a frame has been read. The DMA immediately

continues on the next frame, so this interrupt only ensures that the frame buffer for the previous frame is no

longer required.

Table B-4 Interrupt Clear Register bit assignments (continued)

Bits Name Function

31 43 021

RESERVED

UNDERRUN

VSYNC

BUS_ERROR

DMA_END

Table B-5 Interrupt Mask Register bit assignments

Bits Name Function

[31:4] - Reserved, write as zero, read undefined.

[3] UNDERRUN No data was available to display while DATAEN was active.

This interrupt triggers if the controller does not have pixel data available to drive when

DATAEN is active. When this occurs, the controller drives the default color for the rest of the

screen and attempts to display the next frame correctly.

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ARM AMBA NIC-301 Specifikace Strana 161