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HDLCD controller
ARM DDI 0503F Copyright © 2012-2013 ARM. All rights reserved. B-15
ID062813 Non-Confidential
Configurations Available in all HDLCD controller configurations.
Attributes See Table B-1 on page B-3.
Figure B-15 shows the bit assignments.
Figure B-15 Horizontal Synch Width Register bit assignments
Table B-16 shows the bit assignments.
Horizontal Back Porch Width Register
The H_BACK_PORCH Register characteristics are:
Purpose Holds the width of the interval between the horizontal sync and the first
visible column, counted in pixel clocks.
Usage constraints There are no usage constraints.
Configurations Available in all HDLCD controller configurations.
Attributes See Table B-1 on page B-3.
Figure B-16 shows the bit assignments.
Figure B-16 Horizontal Back Porch Width Register bit assignments
Table B-17 shows the bit assignments.
Horizontal Data Width Register
The H_DATA Register characteristics are:
Purpose Holds the width of the horizontal data area, that is, the number of visible
columns counted in pixel clocks.
31 12 11 0
Reserved H_SYNC
Table B-16 Horizontal Synch Width Register bit assignments
Bits Name Function
[31:12] - Reserved, write as zero, read undefined
[11:0] H_SYNC Horizontal synch width -1
31 12 11 0
Reserved H_BACK_PORCH
Table B-17 Horizontal Synch Width Register bit assignments
Bits Name Function
[31:12] - Reserved, write as zero, read undefined
[11:0] H_BACK_PORCH Horizontal back porch width -1
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