ARM AMBA NIC-301 Specifikace stáhnout pdf (Strana 20)

Hardware Description

ID062813 Non-Confidential

Note

Bus lines with single-headed arrows indicate the direction of control, not the direction of data

flow. That is, each arrow points from bus master to bus slave.

Cortex-A15_A7 MPCore test chip

The test chip includes the following components and interfaces:

• Cortex-A15 dual-core cluster operating at 1GHz:

— Version r2p1.

— 32KB I/D cache.

— NEON and Floating Point Unit (FPU).

— ACP port.

— 1MB L2 cache.

—Dual Program Flow Trace Macrocell (PTM).

• Cortex-A7 triple-core cluster operating at 800MHz:

— Version r0p1.

— 32KB I/D cache.

— NEON and FPU.

— 512KB L2 cache.

—Dual Embedded Trace Macrocell (ETM).

• NIC-301 AXI interconnect operating at 500MHz.

• CCI-400 cache coherent interconnect operating at 500MHz that provides

cache-coherency between the two clusters.

• DMC-400 32-bit Double Data Rate 2 (DDR2) Dynamic Memory

Controller (DMC) interface to the onboard 2GB DDR2 memory.

• PL354 32-bit SMB controller (SMC). This connects to the motherboard

peripherals.

• PL330 Direct Memory Access (DMA) controller.

• 24-bit HDLCD video controller that drives the MMB to the MUXFPGA on

the V2M-P1 Motherboard Express.

• Multiplexed 64-bit AXI master interface.

• 64KB of local on-chip SRAM.

• CoreSight debug and trace interface to the onboard connectors:

— PTM for each Cortex-A15 core.

— ETM for each Cortex-A7 core.

— 16KB ETB.

—DAP.

— Trace Port Interface Unit (TPIU) for real-time trace data.

— JTAG interface for debug.

• Serial Configuration Controller (SCC) interface:

— Interfaces to the Daughterboard Configuration Controller.

— Configures the test chip Phase-Locked Loops (PLLs) during power

up or reset.

• Interrupts interface:

— Connects interrupt signals from the V2M-P1 motherboard to the

Generic Interrupt Controller (GIC) in the test chip.

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