ARM AMBA NIC-301 Specifikace stáhnout pdf (Strana 114)

Programmers Model

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3.4.6 AXI network interconnect, NIC-301

The ACLK signal clocks the internal AXI. The internal AXI operates asynchronously to the

Cortex-A15_A7 cluster by default. You can operate the internal AXI synchronously to the

cluster by selecting SYSCLK to clock the cluster. See Clocks on page 2-24 and Test chip SCC

Table 3-35 provides information on the AXI interconnect implementation.

3.4.7 HDLCD controller

Table 3-36 provides information on the HDLCD controller implementation.

See Appendix B HDLCD controller for a full description of the HDLCD video controller.

3.4.8 Cache Coherent Interconnect, CCI-400

Table 3-37 provides information on the Cache Coherent Interconnect, CCI-400,

implementation.

Table 3-35 AXI network interconnect implementation

Property Value

Memory base address

0x00_2A00_0000

A15 interrupt 128

A7 interrupt 138

Release version ARM PL301 r2p1

Reference documentation

AMBA

Network Interconnect (NIC-301) Technical Reference Manual.

Table 3-36 HDLCD controller implementation

Property Value

Memory base address

0x00_2B00_0000

Interrupt 117

Table 3-37 cache controller implementation

Property Value

Memory base address

0x00_2C09_0000

CCI-400 error IRQ 132

CCI-400 event counter overflow interrupt[4:0] 137:133

ACE-Lite slave port S0 Connects to the CoreSight DAP

ACE-Lite slave port S1 Connects to PL330 DMA

ACE-Lite slave port S2 Connects to HDLCD

ACE slave port S3 Connects to the Cortex-A15 cluster

ACE slave port S4 Connects to the Cortex-A7 cluster

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ARM AMBA NIC-301 Specifikace Strana 114