ARM AMBA NIC-301 Specifikace stáhnout pdf (Strana 17)

Hardware Description

ID062813 Non-Confidential

2.1 CoreTile Express A15×2 A7×3 daughterboard architecture

Figure 2-1 shows a block diagram of the daughterboard.

Figure 2-1 CoreTile Express A15×2 A7×3 daughterboard block diagram

The daughterboard contains the following devices and interfaces:

Cortex-A15_A7 MPCore test chip

Dual-core A15 cluster, version r2p1, operating at 1GHz.

Triple-core A7 cluster, version r0p1, operating at 800MHz.

Daughterboard Configuration Controller

The Daughterboard Configuration Controller communicates with the

Motherboard Configuration Controller (MCC) on the Motherboard Express

μATX. The Daughterboard Configuration Controller and MCC initiate, control,

and configure the test chip and the daughterboard.

Configuration EEPROM

The daughterboard EEPROM contains configuration information for

identification and detection of the daughterboard during power-up and reset.

High-Definition LCD (HDLCD)

HDLCD interface to the Motherboard Express through the MultiMedia Bus

(MMB).

DDR2 memory

The daughterboard supports 2GB of 32-bit DDR2 on-board memory.

CoreTile Express A15x2 A7x3

Daughterboard

DDR2 2GB

(32-bit)

Cortex-A15_A7

Test Chip

DDR2

HDLCD

Interrupts

AXI master

Serial

configuration

Static

Memory Bus

JTAG/SWD

(DAP/TAP)

32-bit trace

Daughterboard

Configuration

Controller

P-JTAG/SWD

Trace Dual

(32-bit trace)

Trace Single

(16-bit trace)

CB SMB MMB

HSB (M)

HDRY

HDRX

Clock

generator

logic

Configuration

EEPROM

1 2 ... 12 13 14 15 16 17 18 19 20 21 22 ... 177 178

Komentáře k této Příručce

Žádné komentáře

ARM AMBA NIC-301 Specifikace Strana 17

Komentáře k této Příručce