
Hardware Description
ARM DDI 0503F Copyright © 2012-2013 ARM. All rights reserved. 2-26
ID062813 Non-Confidential
Figure 2-10 CoreTile Express A15×2 A7×3 daughterboard clocks
Figure 2-10 shows the default inputs for the PLLs. You can independently select SYSREFCLK
as the inputs to any or all of:
• A15 PLL0.
• A15 PLL1.
• A7 PLL0.
• A7 PLL1.
• HDLCD PLL.
HDRY HDRX
CoreTile Express A15x2 A7x3
Daughterboard
HDLCD
Cortex-A15_A7 MPCore Test Chip
DDR
PLL
DMC-400
OSCCLK
5
2GB
DDR2
DDRCLK
CLK[1:0]
nCLK[1:0]
Cortex-A15
MPCore
Cluster
NIC-301 Matrix
Mux/
Demux
Async M
Async SMC
Daughterboard
Configuration
Controller
HSB (M)
OSCCLK
8
OSCCLK
0
OSCCLK
4
PXLREFCLK
DDRREFCLK
HSBM (CLK)
MMB_IDCLK
OSCCLK
6
8MHz
24MHz
OSCCLK
7
HDLCD
PLL
CoreSight trace
and debug
subsystem
DAP
TPIU
TRACECLKA
TRACECLKB
OSCCLK
1
OSCCLK
2
OSCCLK
3
PXLCLK
A15 PLL0
A15 PLL1
SYSPLL
A7 PLL1
A7 PLL0
Cortex-A7
MPCore
Cluster
CPUREFCLK0
CPUREFCLK1
SYSREFCLK
CPUREFCLK3
CPUREFCLK2
CPU_CLK0_A15
CPU_CLK0_A15/2
CPU_CLK2_A7
CPU_CLK2_A7/2
CPU_CLK1_A15
CPU_CLK3_A7
4:1
glitchless
mux
4:1
glitchless
mux
A15_CLK
A7_CLK
ACLK
PCLK
SYSCLK
TRACECLKIN
CCI-400
Interconnect
System
Timer
System
counter
SP805
SMB_CLKI
SMB_CLKO
SMB_REFCLK
REFCLK24MHZ
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