ARM AMBA NIC-301 Specifikace stáhnout pdf (Strana 44)

Hardware Description

ID062813 Non-Confidential

CPUREFCLK3 A7 PLL 1

reference clock

OSCCLK 3 17MHz-40MHz

Default is 40MHz

Reference for CPU_CLK3_A7. This is an alternative

source for A7_CLK, the clock for the Cortex-A7

triple-core cluster.

Default CPU_CLK3_A7 to OSCCLK 3 ratio: 20:1.

SYSREFCLK SYS PLL

reference clock

OSCCLK 7 17MHz-50MHz

Default is 50MHz

Reference for SYSCLK. This is the alternative source

for A15_CLK, the clock for the Cortex-A15

dual-core cluster and for A7_CLK, the clock for the

A7 triple-core cluster.

Default SYSCLK to OSCCLK 7 ratio: 20:1.

Note

Programmable dividers generate the following clocks

from SYSCLK. See Figure 2-11 on page 2-31:

PCLK The CoreSight subsystem clock. The

default value for the programmable

divider is 2. See Test chip SCC

TRACECLKIN

The CoreSight Trace Port Interface

Unit (TPIU) clock. The default value

for the programmable divider is 4.

See Test chip SCC Register 11 on

page 3-27.

ACLK The clock for the internal AXI fabric,

the DMC-400 Dynamic Memory

Controller (DMC) and the

Cache-Coherent Interconnect

(CCI-400).

The default value for the

programmable divider is 2. See Test

chip SCC Register 11 on page 3-27.

These clocks are synchronous with SYSCLK. If you

select SYSCLK as the source for A15_CLK or

A7_CLK, the core operates synchronously with the

CCI-400 interconnect and the NIC-301 matrix.

See Figure 2-10 on page 2-26.

HSBM (CLK) Multiplexed

AXI master

clock

OSCCLK 4 2MHz-40MHz

Default is 40MHz

External AXI master clock.

Table 2-9 Daughterboard OSCCLK clock sources (continued)

Test chip signal Function Source

OSCCLK

frequency

range and default

Description, clocks derived from test chip

signal

1 2 ... 39 40 41 42 43 44 45 46 47 48 49 ... 177 178

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