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HDLCD controller
ARM DDI 0503F Copyright © 2012-2013 ARM. All rights reserved. B-2
ID062813 Non-Confidential
B.1 Introduction
This appendix describes the LCD controller supporting High Definition (HD) resolutions.
The HDLCD controller has the following features:
Resolution of 2048×2048, sufficient for full 1080p HDTV resolution.
Frame buffer:
Supports all common non-indexed RGB formats.
Frame buffer can be placed anywhere in memory.
Scan lines must be a multiple of 8 bytes long, and aligned to 8-byte boundaries.
There are no other restrictions on size or placement. Line pitch is configurable in
multiples of 8 bytes.
Management:
Frame buffer address can be updated at any time, and applies from the next full
frame.
Frame buffer size, color depth, and timing can only be changed while the display is
disabled.
Maskable interrupts:
DMA-end, last part of frame read from bus.
—VSYNC.
Underrun.
—Bus error.
Color depths:
Supports 8 bits per color. Frame buffers with other color depths are truncated or
interpolated to 8 bits per component.
Interfaces:
AMBA 3 APB interface for configuration.
Read-only AXI bus for frame buffer reads.
Standard LCD external interface. All timings and polarities are configurable.
APB, AXI, and pixel clock can run on separate asynchronous clocks.
Buffering:
Internal 2KB buffer.
After underrun, it blanks the rest of the frame and resynchronizes from the next
frame.
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