ARM AMBA NIC-301 Specifikace stáhnout pdf (Strana 60)

Programmers Model

ID062813 Non-Confidential

3.2 Daughterboard memory map

The Cortex-A15_A7 test chip supports the 40-bit Large Physical Address Extension (LPAE).

The programmers model is based on the Cortex-A Series memory map with support for 2GB of

contiguous DDR memory that is located at

0x00_8000_0000

The test chip SMC is located at

0x00_0000_0000

and supports up to six chip selects. The test chip

internal peripherals are located at

0x00_2000_0000

, Cortex-A15_A7 ACP at

0x00_3000_0000

, and

external AXI at

0x00_4000_0000

The memory map supports a remap option at

0x00_0000_0000

that can select SMC or external

AXI.

A typical system boots from SMC CS0 that addresses the motherboard NOR flash 0. See

Remapping memory on page 3-5. After DDR2 configuration is complete, the exception vectors

are moved into the DDR2 area using the CoreSight vector offset registers.

3.2.1 Overview of daughterboard memory map

Figure 3-1 on page 3-4 shows the daughterboard memory map and the remap options. SCC Test

chip SCC Register 4 on page 3-19 controls the remap options. See Remapping memory on

page 3-5.

1 2 ... 55 56 57 58 59 60 61 62 63 64 65 ... 177 178

Žádné komentáře

ARM AMBA NIC-301 Specifikace Strana 60