ARM AMBA NIC-301 Specifikace stáhnout pdf (Strana 118)

Programmers Model

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The watchdog module consists of a 32-bit down counter with a programmable time-out interval

that has the capability to generate an interrupt and a reset signal when it times out. It can be used

to apply a reset to a system in the event of a software failure.

Table 3-41 provides information on the Watchdog implementation.

Note

The watchdog counter is disabled if the core is in the debug state.

3.4.13 System counter

The two generic timers, the system counter, and the system timer, are part of the Cortex-A15

cluster. The system counter provides the Cortex-A15 cluster timers with a real time reference

from reset.

This section describes the system counter. See System timer on page 3-75 for information on the

system timer.

The system counter contains control registers and read registers. See System counter control

Table 3-42 provides information on the system counter implementation.

Table 3-41 Watchdog implementation

Property Value

Memory base address

0x00_2A49_0000

Interrupt 130.

Clock Clocked by REFCLK24MHZ. See Figure 2-10 on page 2-26.

Release version ARM WDOG SP805 r2p0.

Reference documentation

ARM

Watchdog Module (SP805) Technical Reference Manual.

Table 3-42 System counter implementation

Property Value

Memory base address:

System counter control registers

System counter read registers

0x2A43_0000

0x2A80_0000

Clock Clocked by REFCLK24MHZ. See Figure 2-10 on page 2-26.

1 2 ... 113 114 115 116 117 118 119 120 121 122 123 ... 177 178

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ARM AMBA NIC-301 Specifikace Strana 118