ARM AMBA NIC-301 Specifikace stáhnout pdf (Strana 157)

HDLCD controller

ID062813 Non-Confidential

B.2 HDLCD Programmers Model

This section describes the programmers model. It contains the following subsections:

• About the HDLCD controller programmers model

• Register summary

• Register descriptions on page B-4.

B.2.1 About the HDLCD controller programmers model

The following information applies to the HDLCD controller registers:

• The base address is not fixed, and can be different for any particular system

implementation. The offset of each register from the base address is fixed.

• Do not attempt to access reserved or unused address locations. Attempting to access these

locations can result in

UNPREDICTABLE behavior.

• Unless otherwise stated in the accompanying text:

— Do not modify undefined register bits.

— Ignore undefined register bits on reads.

— All register bits are reset to a logic 0 by a system or power-on reset.

• Access type in Table B-1 is described as follows:

RW Read and write.

RO Read only.

WO Write only.

B.2.2 Register summary

Table B-1 shows the registers in offset order from the base memory address.The base memory

address of the HDLCD controller on the Cortex-A15 MPCore test chip is

0x00_2B00_0000

Table B-1 Register summary

Offset Name Type Reset Width Description

0x0000

VERSION RO VERSION 32 Version Register on page B-4

0x0010

INT_RAWSTAT RW

0x0

32 Interrupt Raw Status Register on page B-5

0x0014

INT_CLEAR WO N/A 32 Interrupt Clear Register on page B-6

0x0018

INT_MASK RW

0x0

32 Interrupt Mask Register on page B-7

0x001C

INT_STATUS RO

0x0

32 Interrupt Status Register on page B-8

0x0100

FB_BASE RW

0x0

32 Frame Buffer Base Address Register on page B-9

0x0104

FB_LINE_LENGTH RW

0x0

32 Frame Buffer Line Length Register on page B-9

0x0108

FB_LINE_COUNT RW

0x0

32 Frame Buffer Line Count Register on page B-10

0x010C

FB_LINE_PITCH RW

0x0

32 Frame Buffer Line Pitch Register on page B-11

0x0110

BUS_OPTIONS RW

0x408

32 Bus Options Register on page B-11

0x0200

V_SYNC RW

0x0

32 Vertical Synch Width Register on page B-12

0x0204

V_BACK_PORCH RW

0x0

32 Vertical Back Porch Width Register on page B-13

0x0208

V_DATA RW

0x0

32 Vertical Data Width Register on page B-13

1 2 ... 152 153 154 155 156 157 158 159 160 161 162 ... 177 178

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