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HDLCD controller
ARM DDI 0503F Copyright © 2012-2013 ARM. All rights reserved. B-14
ID062813 Non-Confidential
Configurations Available in all HDLCD controller configurations.
Attributes See Table B-1 on page B-3.
Figure B-13 shows the bit assignments.
Figure B-13 Vertical Data Width Register bit assignments
Table B-14 shows the bit assignments.
Vertical Front Porch Width Register
The V_FRONT_PORCH Register characteristics are:
Purpose Holds the width of the interval between the last visible line and the next
vertical synchronization, counted in number of horizontal scan lines.
Usage constraints There are no usage constraints.
Configurations Available in all HDLCD controller configurations.
Attributes See Table B-1 on page B-3.
Figure B-14 shows the bit assignments.
Figure B-14 Vertical Front Porch Width Register bit assignments
Table B-15 shows the bit assignments.
Horizontal Synch Width Register
The H_SYNCH Register characteristics are:
Purpose Holds the width of the horizontal synch signal, counted in pixel clocks.
Usage constraints There are no usage constraints.
31 12 11 0
Reserved V_DATA
Table B-14 Vertical Data Width Register bit assignments
Bits Name Function
[31:12] - Reserved, write as zero, read undefined
[11:0] V_DATA Vertical data width -1
31 12 11 0
Reserved V_FRONT_PORCH
Table B-15 Vertical Front Porch Width Register bit assignments
Bits Name Function
[31:12] - Reserved, write as zero, read undefined
[11:0] V_FRONT_PORCH Vertical front porch width -1
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