ARM AMBA NIC-301 Specifikace stáhnout pdf (Strana 54)

Hardware Description

ID062813 Non-Confidential

2.10 DDR2 memory interface

The Cortex-A15 DDR2 memory interface uses a DMC-400 Dynamic Memory Controller

(DMC). By default, the DMC runs asynchronously to the AXI matrix so that the AXI

sub-system does not impose frequency limitations on the DMC interface.

Figure 2-15 shows a functional overview of the DDR2 memory interface.

Figure 2-15 DDR2 memory interface

Note

OSCCLK 8 is the source for DDRCLK.

OSCCLK 7 is the source for ACLK.

See Figure 2-10 on page 2-26 and Table 2-9 on page 2-28.

CCI-400

AXI

Domain

DMC-400

Memory

Interface

Test chip

DDR2 Pad

Interface

(PHY)

DDR2 memory interface

32-bit

DDR2

Memory

ACLK

SYS

PLL

DDR

PLL

Cortex-A15_A7 Test Chip

Async

DDRCLK

CoreTile Express A15x2 A7x3

Daughterboard

CK[1:0]

nCK[1:0]

CKE[1:0]

ADDR[15:0]

BA[2:0]

nCAS

nRAS

nWE

DQS[3:0]

nDQS[3:0]

DQ[31:0]

DQM[3:0]

ODT[1:0]

nCS[1:0]

1 2 ... 49 50 51 52 53 54 55 56 57 58 59 ... 177 178

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