ARM AMBA NIC-301 Specifikace stáhnout pdf (Strana 31)

Hardware Description

ID062813 Non-Confidential

CB_nRST Test chip internal

signal nRESET

This is a hard reset from the motherboard that resets boths cores in the Cortex-A15

dual-core cluster and all three cores in the Cortex-A7 triple-core cluster.

The following internal resets, that the SCC reset control register controls, enable

reset of specific sections of the test chip. The multi-signal resets, for example

A15_nCPURESET[1:0], enable reset of specific cores or ETMs, according to the

bits selected in the SCC reset control register.

These internal resets operate independently of nRESET:

• A15_nCPURESET[1:0]

Note

The Cortex

-A15 Technical Reference Manual names this signal as

nCPUPORESET.

• A7_nCPURESET[2:0]

Note

The Cortex

-A7 MPCore

™

Technical Reference Manual names this signal as

nCOREPORESET.

• A15_nCORERESET[1:0].

• A7_nCORERESET[2:0].

• A15_nCXRESET[1:0].

• A15_nDBGRESET[1:0].

• A7_nDBGRESET[2:0].

• A7_nETMRESET[2:0].

• A15_nPRESETDBG.

• A7_nSOCDBGRESET.

• A15_nL2RESET.

• A7_nL2RESET.

• A7_nVSOCRESET.

• A7_nVCORERESET.

• A15_nVSOCRESET.

• A15_nVCORERESET.

See Internal resets on page 2-17.

See the reset control register, Test chip SCC Register 6 on page 3-22, for information

on controlling these internal resets.

See the Cortex

-A15 Technical Reference Manual and the Cortex

-A7 MPCore

™

Technical Reference Manual for information on using the above internal resets.

JTAG nTRST

Test chip internal

signal nTRST

This is the test logic reset to the Cortex-A15 MPCore test chip TAP controller and

the

Daughterboard Configuration Controller.

JTAG nSRST

CB_RSTREQ to

motherboard MCC

If an external source asserts the JTAG nSRST signal, the daughterboard generates a

reset request to the motherboard MCC. The motherboard hardware is reset and the

MCC asserts CB_nRST, and optionally, CB_nPOR

nSRST remains LOW until the reset sequence completes.

CB_RSTREQ

MCC Reset request from the daughterboard to the motherboard.

Test chip watchdogs Test chip internal

nPORESET

If the internal test chip watchdog timers are configured and trigger, they force an

internal test chip nPORESET.

The external system components on the motherboard are not reset.

a. Figure 2-7 on page 2-15 does not include these signals.

Table 2-1 Configuration and reset signals (continued)

Reset source Destination Description

1 2 ... 26 27 28 29 30 31 32 33 34 35 36 ... 177 178

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