ARM Cortex-M3 Uživatelská příručka Strana 105
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- Tabulka s obsahem
- KNIHY
Hodnocené. / 5. Na základě hodnocení zákazníků
Embedded Trace Macrocell
ARM DDI 0337I Copyright © 2005-2008, 2010 ARM Limited. All rights reserved. 10-19
ID072410 Non-Confidential
10.3.9 TraceEnable Start/Stop EmbeddedICE Control Register, ETMTESSEICR
The ETMTESSEICR characteristics are:
Purpose Specifies the EmbeddedICE watchpoint comparator inputs that are used to
control the start/stop resource.
Usage constraints There are no usage constraints.
Configurations This register is only available if the processor is configured to use the
ETM.
Attributes See the register summary in Table 10-6 on page 10-9.
Figure 10-8 shows the ETMTESSEICR bit assignments.
Figure 10-8 ETMTESSEICR bit assignments
Table 10-13 shows the ETMTESSEICR bit assignments.
10.3.10 Device Power-Down Status Register, ETMPDSR
The ETMPDSR characteristics are:
Purpose Indicates the power-down status of the ETM.
[12] Data address comparisons The value of this bit is 1, indicating that data address comparisons are not supported.
[11] Readable registers The value of this bit is 1, indicating that all registers are readable.
[10:3] Extended external input bus The value of these bits is 0, indicating that the extended external input bus is not
implemented.
[2:0] Extended external input
selectors
The value of these bits is 0, indicating that extended external input selectors are not
implemented.
Table 10-12 ETMCCER bit assignments (continued)
Bits Name Function
Reserved, RAZ
31 16 15 0
Reserved, RAZ
4321 4321
19 4 3
Start resource select bitsStop resource select bits
20 18 17 2 1
Table 10-13 ETMTESSEICR bit assignments
Bits Name Function
[31:20] - Reserved, Read-as-zero.
[19:16] Stop resource selection Setting any of these bits to 1 selects the corresponding EmbeddedICE watchpoint input as a
TraceEnable stop resource. Bit [16] corresponds to input 1, bit [17] corresponds to input 2,
bit [18] corresponds to input 3, and bit [19] corresponds to input 4.
[15:4] - Reserved, Read-As-Zero.
[3:0] Start resource selection Setting any of these bits to 1 selects the corresponding EmbeddedICE watchpoint input as a
TraceEnable start resource. Bit [0] corresponds to input 1, bit [1] corresponds to input 2, bit [2]
corresponds to input 3, and bit [3] corresponds to input 4.
- Technical Reference Manual 1
- Cortex-M3 2
- Contents 3
- List of Tables 5
- List of Figures 7
- • About this book on page x 9
- • Feedback on page xiii 9
- About this book 10
- Preface 11
- Other publications 12
- Feedback 13
- Chapter 1 14
- Introduction 14
- 1.1 About the processor 15
- 1.2 Features 16
- 1.3 Interfaces 17
- 1.4 Configurable options 18
- 1.5 Product documentation 19
- 1.6 Product revisions 22
- 0xE000ED14 23
- Chapter 2 25
- Functional Description 25
- 2.1 About the functions 26
- 2.2 Interfaces 28
- Chapter 3 31
- Programmers Model 31
- 3.3 Instruction set summary 34
- — STKALIGN bit to 1 40
- — UNALIGN_TRP bit to 1 40
- 3.4 System address map 41
- LDRH, STR, STRH 42
- 3.5 Write buffer 44
- 3.6 Exclusive monitor 45
- 3.7 Bit-banding 46
- Figure 3-2 Bit-band mapping 47
- 3.9 Exceptions 50
- Chapter 4 52
- System Control 52
- 4.1 About system control 53
- 4.2 Register summary 54
- 4.3 Register descriptions 56
- Chapter 5 58
- Memory Protection Unit 58
- 5.1 About the MPU 59
- 5.3 MPU programmers model 61
- Chapter 6 62
- 6.1 About the NVIC 63
- 6.3 NVIC programmers model 65
- Chapter 7 67
- 7.1 About debug 68
- 0xE000ED00 69
- 0xE00FF000 70
- 7.2 About the AHB-AP 72
- 7.3.2 FPB programmers model 76
- Chapter 8 77
- 8.1 About the DWT 78
- 8.3 DWT Programmers Model 80
- 0x40000000 81
- 0x4F000000 81
- 0x10000000 81
- 0x1F000000 81
- Chapter 9 82
- 9.1 About the ITM 83
- 9.3 ITM programmers model 85
- PRIVMASK 86
- Chapter 10 87
- 10.1 About the ETM 88
- Figure 10-1 ETM block diagram 89
- 10.2.9 Operation 94
- 10.3 ETM Programmers model 95
- Embedded Trace Macrocell 100
- ID072410 Non-Confidential 100
- Reserved 102
- 26 25 24 102
- Trace control enable 102
- Reserved, RAZ 106
- ETM powered up 106
- TRIGGER output value 107
- Chapter 11 109
- Trace Port Interface Unit 109
- 11.1 About the Cortex-M3 TPIU 110
- 11.3 TPIU programmers model 113
- TRIGGER input value 116
- Appendix A 122
- Revisions 122
- Glossary 129
- 0x00000000 132
- 0x1FFFFFFFF 132
- 0xE0040000 133
- 0xE00FFFFF 133
- 0x1FFFFFFF 133
- 0xE0000000 134
- 0xE003FFFF 134
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