ARM ARM926EJ-S Specifikace

Copyright © 2004, 2006 ARM Limited. All rights reserved.ARM DDI 0287BARM926EJ-S Development ChipReference Manual

List of Tablesx Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287BTable 4-5 Bit patterns for GXI state for address channel ...

Memory Map and Memory Configuration 3-26 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287BFigure 3-14 shows the internal bus map

Memory Map and Memory Configuration ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 3-27Figure 3-15 Alias for REMAPSTATIC HIGH

Memory Map and Memory Configuration 3-28 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287BFigure 3-17 shows the internal bus map

Memory Map and Memory Configuration ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 3-293.2.6 APB address mapsFigure 3-19 shows

Memory Map and Memory Configuration 3-30 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287BThe DMA APB address map is listed in Ta

Memory Map and Memory Configuration ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 3-313.2.7 MBX memory mapThe mapping of the

Memory Map and Memory Configuration 3-32 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287B3.3 AHB signals to padsThis section des

Memory Map and Memory Configuration ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 3-33HRESPM1[1:0] Input The transfer respons

Memory Map and Memory Configuration 3-34 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287BHRESPM2[1:0] Input The transfer respons

Part BControllers and Peripherals

List of TablesARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. xiTable 8-1 DMA request and response signal descriptions ...

ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 4-1Chapter 4 AHB MonitorThis chapter describes the AHB Monitor in the ARM926EJ-

AHB Monitor 4-2 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287B4.1 About the AHB monitorThe ARM926EJ-S Development Chip contain

AHB Monitor ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 4-34.2 Functional descriptionThe AHB monitor interface is shown in

AHB Monitor 4-4 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287BAHB Monitor packet formatThere are 33 bits per data packet. To s

AHB Monitor ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 4-5The total number of different NRs and NWs states, that are valid

AHB Monitor 4-6 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287BAHB Cycle State encodingTable 4-3 shows the bit pattern encoding

AHB Monitor ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 4-7S_INCR16, Sequential_INCR16 0 0 0111 - - Y Y Y YNR_EXP1, Expansi

AHB Monitor 4-8 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287BNR_APBCore, APB bridge to Core peripherals011101Y-- -Y-NR_AHBMON

AHB Monitor ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 4-9GXI Cycle States and EncodingThe GXI can perform concurrent read

List of Tablesxii Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287B

AHB Monitor 4-10 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287B4.2.2 Profiling CountersThe Profiling Counters provide informat

AHB Monitor ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 4-11Accessing the Profiling CountersThe profiling counters of each

AHB Monitor 4-12 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287BAs the AMBA AHB specification allows for divergent behavior in

AHB Monitor ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 4-13Counted events on ARM-I layerThe ARM926EJ-S ARM-I BIU performs

AHB Monitor 4-14 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287BCounted events on CLCDC layerThe PrimeCell PL110 CLCDC BIU perf

AHB Monitor ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 4-15Counted events on DMA-0 layerThe PrimeCell PL080 DMAC BIU can p

AHB Monitor 4-16 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287BCounted events on DMA-1 layerThe PrimeCell PL080 DMAC BIU can p

AHB Monitor ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 4-17Counted events on EXPansion layerThe expansion layer is connect

AHB Monitor 4-18 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287BCounted events on ARM-D layerThe ARM926EJ-S ARM-D BIU can perfo

AHB Monitor ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 4-19disables the counters during cycles that the DBGACK is asserted

ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. xiiiList of FiguresARM926EJ-S Development Chip Reference ManualFigure 1-1 Typic

AHB Monitor 4-20 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287BCtArmdPageWalkD Number of read transfers for D-side page table

AHB Monitor ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 4-21Counted Events on the MBX GXI LayerThe MBX connects to the MPMC

AHB Monitor 4-22 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287BMiscellaneous Counted Events with the AHB MonitorTable 4-13 pre

AHB Monitor ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 4-234.3 AHB Monitor registersMany of the registers in the AHB monit

AHB Monitor 4-24 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287BTable 4-14 AHB Monitor registersName Address DescriptionCtArmiR

AHB Monitor ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 4-25CtDma0WrSci0x101D024CCounter. See Ct<layer>Wr<x> on

AHB Monitor 4-26 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287BCtExpWr0x101D0404Counter. See Ct<layer>Wr on page 4-29.Ct

AHB Monitor ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 4-27CtArmdBurstSingle0x101D0508Counter. See Ct<layer>BurstSin

AHB Monitor 4-28 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287BCtGxiRdDWaitThreshold0x101D06384-bit wide R/W Wait Threshold Re

AHB Monitor ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 4-294.3.1 Ct<layer>RdThere are six read count registers. Each

List of Figuresxiv Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287BFigure 3-11 AHB memory map with bridge remap and SMC ...

AHB Monitor 4-30 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287BThese registers contain the total count of completed read trans

AHB Monitor ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 4-314.3.6 Ct<layer>BurstIncrThe read count registers are asso

AHB Monitor 4-32 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287B4.3.9 CtExpBurstWrap8Only the EXPansion bus contains a master t

AHB Monitor ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 4-334.3.12 Ct<layer>BurstIncr16The INCR16 burst count registe

AHB Monitor 4-34 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287B4.3.15 CtArmdPageWalk<x>The ARM926 data AHB interface use

AHB Monitor ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 4-35reset through the AHBMONRstCtrs. The counters associated with t

AHB Monitor 4-36 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287B4.3.20 <layer>WaitThreshold registerThe eight WaitThresho

AHB Monitor ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 4-374.3.22 CtGxiRdThe MBX GXI performs a read transfer completely d

AHB Monitor 4-38 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287B4.3.25 CtGxiPageChangeThe MBX transfers are limited to single w

AHB Monitor ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 4-394.3.29 AHBMONCtrlRegThe AHB Monitor disables all the event coun

List of FiguresARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. xvFigure 17-3 Nonvectored FIQ interrupt logic ...

AHB Monitor 4-40 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287B4.3.33 AHBMONPeriphID 0 to 3Bits [7:0] of the four AHBMONPeriph

AHB Monitor ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 4-414.3.34 AHBMONPCellIDBits [7:0] of the four AHBMONPCellID[3:0] r

AHB Monitor 4-42 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287B4.4 AHB Monitor signals on padsThe output signals are shown in

ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 5-1Chapter 5 Color LCD Controller (CLCDC)This chapter describes the display con

Color LCD Controller (CLCDC) 5-2 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287B5.1 About the CLCDCThe PrimeCell Smart Color LC

Color LCD Controller (CLCDC) ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 5-3Besides data formatting, the CLCDC provides a s

Color LCD Controller (CLCDC) 5-4 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287B5.2 Functional descriptionSimplified block diag

Color LCD Controller (CLCDC) ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 5-5Figure 5-2 CLCDC block diagramClock andresetcon

Color LCD Controller (CLCDC) 5-6 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287B5.2.1 RegistersThe base address of the ARM Prim

Color LCD Controller (CLCDC) ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 5-75.3 Hardware cursor extension to PL110The PL110

List of Figuresxvi Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287B

Color LCD Controller (CLCDC) 5-8 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287BOperationAll cursor programming registers are a

Color LCD Controller (CLCDC) ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 5-9MovementThe following descriptions assume that

Color LCD Controller (CLCDC) 5-10 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287BBecause the ClcdCrsrXY Register values are pos

Color LCD Controller (CLCDC) ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 5-11Image formatThe LCD frame buffer supports thre

Color LCD Controller (CLCDC) 5-12 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287BFor 32x32 bit pixels, four cursors are held in

Color LCD Controller (CLCDC) ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 5-13Table 5-6 and Table 5-7 on page 5-14 list the

Color LCD Controller (CLCDC) 5-14 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287BSoftware format for Windows CEThe software low

Color LCD Controller (CLCDC) ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 5-15Table 5-8 32x32 software mask storageExternal

Color LCD Controller (CLCDC) 5-16 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287BPixel encodingEach pixel of the cursor require

Color LCD Controller (CLCDC) ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 5-175.3.2 Hardware cursor registersTable 5-1 lists

ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. xviiPrefaceThis preface introduces the ARM926EJ-S Development Chip Reference Ma

Color LCD Controller (CLCDC) 5-18 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287BCursor Image RAM RegisterThe CursorImage Regis

Color LCD Controller (CLCDC) ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 5-19Table 5-2 lists the register bit assignments.T

Color LCD Controller (CLCDC) 5-20 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287BCursor Configuration RegisterThe ClcdCrsrConfi

Color LCD Controller (CLCDC) ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 5-21Figure 5-9 shows the register bit assignments.

Color LCD Controller (CLCDC) 5-22 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287BTable 5-5 lists the register bit assignments.I

Color LCD Controller (CLCDC) ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 5-23Table 5-6 lists the register bit assignments.D

Color LCD Controller (CLCDC) 5-24 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287BTable 5-7 lists the register bit assignments.C

Color LCD Controller (CLCDC) ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 5-25Cursor Raw Interrupt Status RegisterThe ClcdCr

Color LCD Controller (CLCDC) 5-26 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287BCursor Masked Interrupt Status RegisterThe Clc

Color LCD Controller (CLCDC) ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 5-27Peripheral Identification RegistersThe CLCDPer

Preface xviii Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287BAbout this documentThis document provides an overview of the ARM92

Color LCD Controller (CLCDC) 5-28 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287BThe CLCDPeriphID0 Register is read-only. It is

Color LCD Controller (CLCDC) ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 5-29PrimeCell Identification RegistersThe CLCDPCel

Color LCD Controller (CLCDC) 5-30 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287BThe CLCDPCellID2 Register is read-only. It is

Color LCD Controller (CLCDC) ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 5-315.4 CLCD signals on padsThe only external inpu

Color LCD Controller (CLCDC) 5-32 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287B

ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 6-1Chapter 6 MOVE CoprocessorThis chapter describes the MOVE graphic coprocesso

MOVE Coprocessor 6-2 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287B6.1 About the MOVE CoprocessorThe MOVE coprocessor is a vid

MOVE Coprocessor ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 6-3Figure 6-1 MOVE overviewControl logicRegisterbankDatapathMO

MOVE Coprocessor 6-4 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287B

ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 7-1Chapter 7 MBX HR-S Graphics AcceleratorThis chapter describes the ARM MBX HR

Preface ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. xixChapter 9 General Purpose Input Output (GPIO) Read this chapter for

MBX HR-S Graphics Accelerator 7-2 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287B7.1 About the ARM MBX HR-SThe ARM MBX HR-S is

MBX HR-S Graphics Accelerator ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 7-3The ARM MBX HR-S operates on 3D scene data (se

MBX HR-S Graphics Accelerator 7-4 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287B7.1.1 Features of the ARM MBX HR-SThe ARM MBX

MBX HR-S Graphics Accelerator ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 7-57.1.2 Functional overviewPowerVR technology is

MBX HR-S Graphics Accelerator 7-6 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287B7.2 Memory map and registersThe MBX HR-S memor

MBX HR-S Graphics Accelerator ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 7-77.2.3 GX port memory interfaceThe MBX HR-S con

MBX HR-S Graphics Accelerator 7-8 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287BFigure 7-2 MMU address translationBits [31:12]

ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 8-1Chapter 8 Direct Memory Access Controller (DMAC)This chapter describes DMAC

Direct Memory Access Controller (DMAC) 8-2 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287B8.1 About the Direct Memory Access Co

Direct Memory Access Controller (DMAC) ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 8-3• Programmable DMA burst size. The DM

ii Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287BARM926EJ-S Development Chip Reference ManualCopyright © 2004, 2006 ARM Limit

Preface xx Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287BTypographical conventionsThe following typographical conventions are

Direct Memory Access Controller (DMAC) 8-4 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287B8.2 Functional descriptionThe block d

Direct Memory Access Controller (DMAC) ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 8-58.2.1 Peripheral integrationThe alloc

Direct Memory Access Controller (DMAC) 8-6 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287B8.2.2 RegistersThe PrimeCell DMAC ena

Direct Memory Access Controller (DMAC) ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 8-78.3 DMA signals on padsThe pad input

Direct Memory Access Controller (DMAC) 8-8 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287B

ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 9-1Chapter 9 General Purpose Input Output (GPIO)This chapter describes the GPIO

General Purpose Input Output (GPIO) 9-2 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287B9.1 About the ARM PrimeCell GPIO (PL061)

General Purpose Input Output (GPIO) ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 9-39.2 Functional descriptionFigure 9-1 sho

General Purpose Input Output (GPIO) 9-4 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287BNote For GPIO3, the GPAFIN[6:0] signals

General Purpose Input Output (GPIO) ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 9-59.3 GPIO signals on padsTable 9-2 descri

Preface ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. xxiThe following publications provide reference information about the A

General Purpose Input Output (GPIO) 9-6 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287B

ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 10-1Chapter 10 Multi-Port Memory Controller (MPMC)This chapter describes the MP

Multi-Port Memory Controller (MPMC) 10-2 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287B10.1 About the ARM PrimeCell MPMC (GX17

Multi-Port Memory Controller (MPMC) ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 10-3• Power-saving modes dynamically contro

Multi-Port Memory Controller (MPMC) 10-4 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287B10.1.2 Supported dynamic memory devices

Multi-Port Memory Controller (MPMC) ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 10-510.1.3 Supported static memory devicesT

Multi-Port Memory Controller (MPMC) 10-6 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287B10.2 Functional descriptionFigure 10-1

Multi-Port Memory Controller (MPMC) ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 10-710.2.1 Implementation detailsThe follow

Multi-Port Memory Controller (MPMC) 10-8 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287B10.3 MPMC signals on padsThe pad interf

Multi-Port Memory Controller (MPMC) ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 10-9nMPMCRASOUT Output Pad Row address str

Preface xxii Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287B• ARM PrimeCell Watchdog Controller (SP805) Technical Reference Man

Multi-Port Memory Controller (MPMC) 10-10 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287B

ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 11-1Chapter 11 Real-Time Clock (RTC)This chapter describes the Real Time Clock

Real-Time Clock (RTC) 11-2 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287B11.1 About the Real Time ClockThe PrimeCell Real Time

Real-Time Clock (RTC) ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 11-311.2 Functional descriptionThe release version used i

Real-Time Clock (RTC) 11-4 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287B11.2.1 RegistersThe base address of the PrimeCell RTC

ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 12-1Chapter 12 Smart Card Interface (SCI)This chapter describes the SCI in the

Smart Card Interface (SCI) 12-2 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287B12.1 About the ARM SCIThe PrimeCell Smart Card I

Smart Card Interface (SCI) ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 12-312.1.1 Programmable parametersThe following key

Smart Card Interface (SCI) 12-4 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287B12.2 Functional descriptionThe block diagram of

Smart Card Interface (SCI) ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 12-512.2.3 InterruptsThere are fifteen interrupts ge

Preface ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. xxiiiFeedbackARM Limited welcomes feedback both on the ARM926EJ-S Devel

Smart Card Interface (SCI) 12-6 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287B12.3 SCI signals on padsThe SCI interface signal

ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 13-1Chapter 13 Synchronous Static Memory Controller (SSMC)This chapter describe

Synchronous Static Memory Controller (SSMC) 13-2 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287B13.1 About the ARM PrimeCell SS

Synchronous Static Memory Controller (SSMC) ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 13-3• external asynchronous wait co

Synchronous Static Memory Controller (SSMC) 13-4 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287B13.1.3 Supported memory devices

Synchronous Static Memory Controller (SSMC) ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 13-513.2 Functional descriptionThe

Synchronous Static Memory Controller (SSMC) 13-6 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287BIf the select signal CFGMPMCnSM

Synchronous Static Memory Controller (SSMC) ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 13-7Figure 13-3 Data multiplexorMPM

Synchronous Static Memory Controller (SSMC) 13-8 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287B13.2.1 Implementation detailsTa

Synchronous Static Memory Controller (SSMC) ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 13-913.3 SSMC signals on padsTable

Preface xxiv Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287B

Synchronous Static Memory Controller (SSMC) 13-10 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287BnSMCS6 Output Chip select for

ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 14-1Chapter 14 Synchronous Serial Port (SSP)This chapter describes the SSP in t

Synchronous Serial Port (SSP) 14-2 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287B14.1 About the ARM PrimeCell SSP (PL022)The P

Synchronous Serial Port (SSP) ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 14-3• Programmable choice of interface operation,

Synchronous Serial Port (SSP) 14-4 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287B14.2 Functional descriptionThis section descr

Synchronous Serial Port (SSP) ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 14-514.2.2 RegistersThe base address of the Prime

Synchronous Serial Port (SSP) 14-6 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287B14.3 SSP signals on padsThe signals connected

ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 15-1Chapter 15 Dual Timer/CountersThis chapter describes the SP804 timer/counte

Dual Timer/Counters 15-2 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287B15.1 About the ARM Dual-Timer module (SP804)The ARM Dua

Dual Timer/Counters ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 15-315.2 Functional descriptionThis section gives a basic o

Part AIntroduction and Configuration

Dual Timer/Counters 15-4 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287BFigure 15-1 shows a simplified block diagram of the mod

Dual Timer/Counters ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 15-515.2.2 Programmable parametersThe following Dual-Timer

Dual Timer/Counters 15-6 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287B

ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 16-1Chapter 16 UART ControllerThis chapter describes the UART peripherals in th

UART Controller 16-2 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287B16.1 About the ARM PrimeCell UART (PL011)The PrimeCell UART

UART Controller ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 16-3• Independent masking of transmit FIFO, receive FIFO, recei

UART Controller 16-4 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287B16.2 Functional descriptionFigure 16-1 shows a block diagra

UART Controller ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 16-516.2.1 Clock signalsThe UARTs can be clocks from an interna

UART Controller 16-6 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287BProgrammable parametersThe following key parameters are pro

UART Controller ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 16-716.2.5 Implementation detailsThe following inputs are tied

UART Controller 16-8 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287B16.3 UART signals on padsThe signals connected to pads are

UART Controller ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 16-9nUART0DTR Output UART Data Terminal Ready modem status sign

UART Controller 16-10 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287B

ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 17-1Chapter 17 Vectored Interrupt Controller (VIC)This chapter describes the ve

Vectored Interrupt Controller (VIC) 17-2 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287B17.1 About the ARM PrimeCell Vectored I

Vectored Interrupt Controller (VIC) ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 17-3Only a single FIQ source at a time is g

Vectored Interrupt Controller (VIC) 17-4 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287B17.2 Functional descriptionFigure 17-1

Vectored Interrupt Controller (VIC) ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 17-517.2.1 Interrupt request logicThe inter

Vectored Interrupt Controller (VIC) 17-6 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287B17.2.2 Nonvectored FIQ interrupt logicT

Vectored Interrupt Controller (VIC) ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 17-717.2.4 Vectored interrupt blockThere ar

ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 1-1Chapter 1 IntroductionThis chapter introduces the ARM926EJ-S Development Chi

Vectored Interrupt Controller (VIC) 17-8 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287B17.2.5 Interrupt priority logicThe inte

Vectored Interrupt Controller (VIC) ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 17-917.2.6 Vectored interruptsA vectored in

Vectored Interrupt Controller (VIC) 17-10 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287B17.2.9 Implementation detailsThe tied

Vectored Interrupt Controller (VIC) ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 17-1117.3 VIC signals on padsThe interrupt

Vectored Interrupt Controller (VIC) 17-12 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287B

ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 18-1Chapter 18 ARM Vector Floating Point Coprocessor (VFP9)This chapter describ

ARM Vector Floating Point Coprocessor (VFP9) 18-2 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287B18.1 About the VFP9-S coproces

ARM Vector Floating Point Coprocessor (VFP9) ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 18-318.2 ARMv5TE coprocessor exten

ARM Vector Floating Point Coprocessor (VFP9) 18-4 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287B18.3 VFP9-S system control and

ARM Vector Floating Point Coprocessor (VFP9) ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 18-5Access to the FPEXC, FPINST, a

Introduction 1-2 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287B1.1 About the ARM926EJ-S Development ChipThe ARM926EJ-S Develop

ARM Vector Floating Point Coprocessor (VFP9) 18-6 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287B18.4 Modes of operationThe VFP

ARM Vector Floating Point Coprocessor (VFP9) ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 18-7• A float-to-integer conversio

ARM Vector Floating Point Coprocessor (VFP9) 18-8 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287B18.4.4 RunFast ModeRunFast mod

ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 19-1Chapter 19 Watchdog TimerThis chapter describes the Watchdog timer in the A

Watchdog Timer 19-2 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287B19.1 About the Watchdog module (SP805)The Watchdog module is

Watchdog Timer ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 19-319.2 Functional descriptionFigure 19-1 shows a simplified bl

Watchdog Timer 19-4 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287Bdisables write accesses to all registers except the Lock Reg

ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. A-1Appendix A Signals on PadsThis appendix lists the signals on the ARM926EJ-S

Signals on Pads A-2 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287BA.1 Pad signals by functionTable A-1 lists the pad signals a

Signals on Pads ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. A-3AHB M1 HADDRM1[9] Address bus T 8 AJ33AHB M1 HADDRM1[10] Add

Introduction ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 1-3The block diagram in Figure 1-2 shows the internal buses and th

Signals on Pads A-4 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287BAHB M1 HBURSTM1[2] Transfer burst length T 8 AD34AHB M1 HBUS

Signals on Pads ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. A-5AHB M1 HDATAM1[23] Data bus B 8 V28AHB M1 HDATAM1[24] Data b

Signals on Pads A-6 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287BAHB M2 HADDRM2[2] Address bus T 8 M33AHB M2 HADDRM2[3] Addre

Signals on Pads ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. A-7AHB M2 HADDRM2[27] Address bus T 8 M29AHB M2 HADDRM2[28] Add

Signals on Pads A-8 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287BAHB M2 HDATAM2[16] Data bus B 8 C30AHB M2 HDATAM2[17] Data b

Signals on Pads ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. A-9AHB M2 HSIZEM2[0] Transfer size T 8 K30AHB M2 HSIZEM2[1] Tra

Signals on Pads A-10 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287BAHB S HADDRS[20] Address bus I - F5AHB S HADDRS[21] Address

Signals on Pads ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. A-11AHB S HDATAS[10] Data bus B 8 B11AHB S HDATAS[11] Data bus

Signals on Pads A-12 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287BAHB S HPROTS[2] Protection Control I - H1AHB S HPROTS[3] Pr

Signals on Pads ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. A-13AHB Monitor AHBMONITOR[14] Debug information O 8 F23AHB Mon

ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. iiiConformance NoticesThis section contains conformance notices. Federal Commu

Introduction 1-4 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287B1.2 Functional descriptionThe ARM926EJ-S Development Chip compr

Signals on Pads A-14 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287BCLCDC CLD[2] Data bus O 4 AL23CLCDC CLD[3] Data bus O 4 AP2

Signals on Pads ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. A-15CLCDC CLPOWER Panel power enable O 4 AM22Clock HCLKM1 Async

Signals on Pads A-16 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287BDMAC DMACLBREQ[0] Last Burst Transfer Request I - N1DMAC DM

Signals on Pads ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. A-17ETM ETMEXTOUT[0] Debug cross trigger support O 12 A14ETM ET

Signals on Pads A-18 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287BGPIO 0 GP0[1] General Purpose I/O B 8 AJ5GPIO 0 GP0[2] Gene

Signals on Pads ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. A-19GPIO 3 GP3[2] General Purpose I/O B 4 AL6GPIO 3 GP3[3] Gene

Signals on Pads A-20 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287BMPMC MPMCADDR[5] Address bus O 12 AA4MPMC MPMCADDR[6] Add

Signals on Pads ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. A-21MPMC MPMCDATA[6] Data bus B 8 AD4MPMC MPMCDATA[7] Data bu

Signals on Pads A-22 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287BMPMC MPMCDATA[31] Data bus B 8 AE7MPMC MPMCDQM[0] Data ma

Signals on Pads ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. A-23Power VDDC[6] Core Power PC - AH3Power VDDC[7] Core Power P

Introduction ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 1-5AHB Monitor The AHB Monitor block outputs transaction informati

Signals on Pads A-24 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287BPower VDDIO[3] I/O Power PIO - AL1Power VDDIO[4] I/O Power

Signals on Pads ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. A-25Power VDDIO[28] I/O Power PIO - D19Power VDDIO[29] I/O Powe

Signals on Pads A-26 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287BPower VDDIO[53] I/O Power PIO - D34Power VDDIO[54] I/O Powe

Signals on Pads ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. A-27SSMC nSTATICCS[2] Chip select O 8 AN20SSMC nSTATICCS[3] Chi

Signals on Pads A-28 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287BSSMC SMADDR[19] Address bus O 12 AN17SSMC SMADDR[20] Addres

Signals on Pads ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. A-29SSMC SMDATA[12] Data bus B 8 AK12SSMC SMDATA[13] Data bus B

Signals on Pads A-30 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287BSSP SSPCLKIN Clock input I - C20SSP SSPCLKOUT Clock output

Signals on Pads ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. A-31UART 2 UART2RXD Received serial data I - AJ29UART 2 UART2TX

Signals on Pads A-32 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287B

ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. B-1Appendix B Mechanical and Electrical SpecificationsThis appendix contains th

Introduction 1-6 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287BDirect Memory Access Controller (DMAC) Direct memory access can

Mechanical and Electrical Specifications B-2 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287BB.1 Mechanical detailsFigure B-1 sh

Mechanical and Electrical Specifications ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. B-3B.2 Electrical specificationThis se

Mechanical and Electrical Specifications B-4 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287BB.2.2 Power estimationTable B-3 sho

ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. C-1Appendix C Timing SpecificationThis appendix provides the AC timing paramete

Timing Specification C-2 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287BC.1 About the timing parametersFigure C-1 shows the par

Timing Specification ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. C-3C.2 AHB bus timingTable C-1 lists the timing for the AH

Timing Specification C-4 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287BC.3 Memory timingTable C-2 shows the memory timing. For

Timing Specification ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. C-5C.4 Peripheral timingTable C-3 shows the peripheral and

Timing Specification C-6 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287B

ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. Index-1IndexThe items in this index are listed in alphabetical order, with symb

Introduction ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 1-7For more information on the timers, see the ARM Dual-Timer Modu

IndexIndex-2 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287BSCI 12-6signals 2-32SSMC 13-9SSP 14-4Watchdog 19-3CoreDMA

IndexARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. Index-3RRTC 1-6base address 11-4input clock 11-2reserved locations

IndexIndex-4 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287Bpin numbering B-2SSMC 1-5features 13-2I/O connections 13-5p

Introduction 1-8 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287BFor more information on the CLCDC, see the ARM PrimeCell Color

Introduction ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 1-91.3 External interfacesThe ARM926EJ-S Development Chip supports

Introduction 1-10 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287B1.3.1 External memory supportTwo memory interfaces are provide

Introduction ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 1-11Default memory mapThe default memory map is divided into the r

Introduction 1-12 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287BFigure 1-3 Default system bus memory map for ARM DATA AHB bus0

Introduction ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 1-131.3.2 DMA supportThe PrimeCell Dual-Master DMAC is provided to

iv Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287B

Introduction 1-14 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287B

ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 2-1Chapter 2 System Controller and Configuration LogicThis chapter describes th

System Controller and Configuration Logic 2-2 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287B2.1 About the System ControllerThe

System Controller and Configuration Logic ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 2-32.1.2 Interrupt response modeTo en

System Controller and Configuration Logic 2-4 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287B2.1.4 Low battery handlingTwo inpu

System Controller and Configuration Logic ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 2-5Figure 2-1 Enable signal generatio

System Controller and Configuration Logic 2-6 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287BThe Watchdog module enable is gene

System Controller and Configuration Logic ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 2-72.1.8 System mode controlA system

System Controller and Configuration Logic 2-8 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287BIf the nPOR input is activated, th

System Controller and Configuration Logic ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 2-9It is possible to override the mod

ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. vContentsARM926EJ-S Development Chip Reference ManualPrefaceAbout this document

System Controller and Configuration Logic 2-10 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287BDOZE modeIn DOZE mode, the system

System Controller and Configuration Logic ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 2-11PLL control transition state, PLL

System Controller and Configuration Logic 2-12 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287BCore clock controlTo enable the s

System Controller and Configuration Logic ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 2-132.2 Clock controlThe operation of

System Controller and Configuration Logic 2-14 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287BAn example of external clock sour

System Controller and Configuration Logic ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 2-15The clock and reset controller ha

System Controller and Configuration Logic 2-16 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287BIn the example shown in Figure 2-

System Controller and Configuration Logic ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 2-172.2.2 SDRAM interaction with freq

System Controller and Configuration Logic 2-18 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287B2.2.3 Peripheral clock selectionT

System Controller and Configuration Logic ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 2-192.3 External configuration signal

Contentsvi Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287BChapter 3 Memory Map and Memory Configuration3.1 Overview of the AMBA

System Controller and Configuration Logic 2-20 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287BTable 2-3 Configuration signal de

System Controller and Configuration Logic ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 2-21CFGREMAPDYEXEN ARM926EJ-S Develop

System Controller and Configuration Logic 2-22 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287BCFGHCLKEXTDIVSEL[2:0] Clock and r

System Controller and Configuration Logic ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 2-23CFGAHBSASYNC On-chip AHB bridge a

System Controller and Configuration Logic 2-24 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287BFigure 2-6 Power-on configuration

System Controller and Configuration Logic ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 2-252.4 JTAG logicThe JTAG interface

System Controller and Configuration Logic 2-26 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287BFigure 2-7 JTAG Test Access PortE

System Controller and Configuration Logic ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 2-27Figure 2-8 Multi-ICE synchronizat

System Controller and Configuration Logic 2-28 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287B2.5 Implementation details for th

System Controller and Configuration Logic ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 2-29The following system controller i

ContentsARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. viiChapter 12 Smart Card Interface (SCI)12.1 About the ARM SCI ...

System Controller and Configuration Logic 2-30 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287B2.6 Control, configuration, and t

System Controller and Configuration Logic ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 2-31Table 2-6 lists the reset and con

System Controller and Configuration Logic 2-32 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287BTable 2-7 lists the clock signals

System Controller and Configuration Logic ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 2-33Table 2-8 lists the JTAG signals.

System Controller and Configuration Logic 2-34 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287B

ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 3-1Chapter 3 Memory Map and Memory ConfigurationThis chapter describes the AMBA

Memory Map and Memory Configuration 3-2 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287B3.1 Overview of the AMBA buses in the AR

Memory Map and Memory Configuration ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 3-3Six AHB buses are provided:ARM I AHB Th

Memory Map and Memory Configuration 3-4 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287BFigure 3-1 Bus matrix configurationSyste

Memory Map and Memory Configuration ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 3-5The ARM926EJ-S PXP Slave Expansion AHB i

Contentsviii Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287BAppendix C Timing SpecificationC.1 About the timing parameters ...

Memory Map and Memory Configuration 3-6 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287B3.1.3 AHB restrictionsUsing a multilayer

Memory Map and Memory Configuration ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 3-7Figure 3-2 AHB M1 interface+%85670287&g

Memory Map and Memory Configuration 3-8 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287BFigure 3-3 AHB M2 interface+%85670287&g

Memory Map and Memory Configuration ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 3-9The bridge AHB master output signals dri

Memory Map and Memory Configuration 3-10 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287BThe multiplexor control determines whic

Memory Map and Memory Configuration ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 3-11the bridge are combinatorial. As there

Memory Map and Memory Configuration 3-12 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287BThe bridge can operate in four modes th

Memory Map and Memory Configuration ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 3-13Figure 3-4 AHB S interface+%85676,1>

Memory Map and Memory Configuration 3-14 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287B3.1.5 EndiannessThe ARM926EJ-S Developm

Memory Map and Memory Configuration ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 3-153.2 Memory map optionsSupporting severa

ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. ixList of TablesARM926EJ-S Development Chip Reference ManualChange history ...

Memory Map and Memory Configuration 3-16 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287BFigure 3-5 Memory control signalsARM926

Memory Map and Memory Configuration ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 3-173.2.1 TCMThe ARM926EJ-S Development Chi

Memory Map and Memory Configuration 3-18 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287BFigure 3-6 Default AHB memory map with

Memory Map and Memory Configuration ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 3-19The memory map for control signals CFGB

Memory Map and Memory Configuration 3-20 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287B3.2.4 Bridge remappingThe default decod

Memory Map and Memory Configuration ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 3-21If CFGBRIDGEMEMMAP is LOW, however, the

Memory Map and Memory Configuration 3-22 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287BFigure 3-10 shows the normal decoding.F

Memory Map and Memory Configuration ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 3-23The memory map for bridge remapping is

Memory Map and Memory Configuration 3-24 Copyright © 2004, 2006 ARM Limited. All rights reserved. ARM DDI 0287BIf the SSMC is not used, part of the st

Memory Map and Memory Configuration ARM DDI 0287B Copyright © 2004, 2006 ARM Limited. All rights reserved. 3-253.2.5 AHB memory alias for low memoryNo