ARM Cortex R4F Specifikace stáhnout pdf (Strana 1)

Application Report

SPNA106– September 2011

Initialization of Hercules™ ARM

Cortex™-R4F

Microcontrollers

Sunil Oak........................................................................................................................................

ABSTRACT

This application report provides a brief overview and initialization procedure of the TMS570LS31x series

and the RM4x series of microcontrollers in the Hercules family. "Hercules MCU" will be used henceforth in

this document to refer to any part in these series of microcontrollers.

The document also shows code fragments from source files that are generated using the nowGen tool. All

code constructs used in this document are defined in header files also generated by the same utility.

Contents

1 Block Diagram ............................................................................................................... 3

2 Standard Initialization Sequence for Hercules Microcontrollers ...................................................... 4

3 References ................................................................................................................. 32

List of Figures

1 Device Block Diagram...................................................................................................... 3

2 Color Legend for Block Diagram.......................................................................................... 3

3 FMPLL Block Diagram ..................................................................................................... 5

4 PLL Control Register 1 (PLLCTL1) Address = 0xFFFFFF70 ......................................................... 6

5 PLL Control Register 2 (PLLCTL2) Address = 0xFFFFFF74 ......................................................... 7

6 Clock Source Disable Register (CSDIS) Address = 0xFFFFFF30 ................................................... 8

7 Clock Source Disable Set Register (CSDISSET) Address = 0xFFFFFF34 ......................................... 9

8 Clock Source Disable Clear Register (CSDISCLR) Address = 0xFFFFFF38....................................... 9

9 Flash Read Control Register (FRDCNTL) Address = 0xFFF87000 ................................................ 14

10 Flash State Machine Write Enable Control Register (FSM_WR_ENA) Address = 0xFFF87288 ............... 15

11 Flash EEPROM Configuration Register (EEPROM_CONFIG) Address = 0xFFF872B8 ........................ 15

12 Flash Bank Fall-Back Control Register (FBFALLBACK) Address = 0xFFF87040................................ 16

13 Flash Bank Access Control Register (FBAC) Address = 0xFFF8703C ............................................ 17

14 Flash Pump Access Control Register 1 (FPAC1) Address = 0xFFF87048........................................ 18

15 Flash Pump Access Control Register 2 (FPAC2) Address = 0xFFF8704C ....................................... 18

16 GCLK, HCLK , VCLKx Source Register (GHVSRC) Address = 0xFFFFFF48 .................................... 19

17 Asynchronous Clock Source Register (VCLKASRC) Address = 0xFFFFFF4C................................... 20

18 Asynchronous Clock Configuration Register 1 (VCLKACON1) Address = 0xFFFFE140........................ 20

19 RTI Clock Source Register (RCLKSRC) Address = 0xFFFFFF50.................................................. 21

20 Peripheral Clock Control Register (CLKCNTL) Address = 0xFFFFFFD0.......................................... 21

21 Clock Control Register 2 (CLK2CNTL) Address = 0xFFFFE13C ................................................... 22

22 Memory Hardware Initialization Global Control Register (MINITGCR) Address = 0xFFFFFF5C............... 24

23 Memory Self-Test / Initialization Control Register (MSIENA) Address = 0xFFFFFF60 .......................... 25

24 Memory Self-Test / Initialization Status Register (MSTCGSTAT) Address = 0xFFFFFF68 ..................... 25

Hercules is a trademark of Texas Instruments.

Cortex is a trademark of ARM Limited.

ARM is a registered trademark of ARM Limited.

All other trademarks are the property of their respective owners.

SPNA106– September 2011 Initialization of Hercules™ ARM

Cortex™-R4F Microcontrollers

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1 2 3 4 5 6 ... 32 33

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Strany 1 - Microcontrollers

Application ReportSPNA106– September 2011Initialization of Hercules™ ARM®Cortex™-R4FMicrocontrollersSunil Oak...

Strany 2

Standard Initialization Sequence for Hercules Microcontrollerswww.ti.com2.4 Configure Oscillator MonitorThe HF LPO clock source is used as a reference

Strany 3 - #1 #2 #1

www.ti.comStandard Initialization Sequence for Hercules Microcontrollers2.5 Enabling Floating-Point Coprocessor (FPU)The floating-point coprocessor is

Strany 4

Standard Initialization Sequence for Hercules Microcontrollerswww.ti.commov r11, #0x0000mov r12, #0x0000; Switch back to Supervisor Mode (M = 0b10011)

Strany 5 - 2.2 Configure PLLs

www.ti.comStandard Initialization Sequence for Hercules MicrocontrollersWhen the return stack detects a taken return instruction, the PFU issues an in

Strany 6 - PLLMUL[15:0]

Standard Initialization Sequence for Hercules Microcontrollerswww.ti.com2.8 Configure Flash AccessThe Flash memory on the Hercules series microcontrol

Strany 7

www.ti.comStandard Initialization Sequence for Hercules MicrocontrollersFigure 10. Flash State Machine Write Enable Control Register (FSM_WR_ENA) Addr

Strany 8 - 2.3 Enable Clock Sources

Standard Initialization Sequence for Hercules Microcontrollerswww.ti.com2.9 Configure Flash Bank and Pump Power ModesThe Flash banks and pump used on

Strany 9

www.ti.comStandard Initialization Sequence for Hercules MicrocontrollersEach of the BANKPWRx fields configures the fall-back mode for a single Flash b

Strany 10 - Submit Documentation Feedback

Standard Initialization Sequence for Hercules Microcontrollerswww.ti.comflashWREG->FMAC = 0x00000000; // Select flash bank0flashWREG->FBAC |= 0x

Strany 11

www.ti.comStandard Initialization Sequence for Hercules MicrocontrollersflashWREG->FPAC2 = 0x000000FF; // PSLEEP = 255 * 16 HCLK cycles2.10 Clock D

Strany 12

www.ti.com25 VIM Interrupt Address Memory Map ... 2726 FIQ/IRQ Contro

Strany 13 - 2.7 Reset Handler

Standard Initialization Sequence for Hercules Microcontrollerswww.ti.comTable 11. GCLK, HCLK , VCLKx Source Register (GHVSRC) Field Descriptions (cont

Strany 14 - 2.8 Configure Flash Access

www.ti.comStandard Initialization Sequence for Hercules MicrocontrollersThe asynchronous clock source register (VCLKASRC) is shown in Figure 19.Figure

Strany 15

Standard Initialization Sequence for Hercules Microcontrollerswww.ti.comsystemREG1->CLKCNTL |= 0x00000000U ; // VCLK2 = HCLK/1temp = systemREG1->

Strany 16

www.ti.comStandard Initialization Sequence for Hercules Microcontrollers2.14 Enable Response to ECC Errors in Flash Module and TCRAM ModuleThe flash m

Strany 17

Standard Initialization Sequence for Hercules Microcontrollerswww.ti.com2.18 Run Self-Test on the Flash Module SECDED LogicThe Flash module reads the

Strany 18 - Reserved

www.ti.comStandard Initialization Sequence for Hercules MicrocontrollersFigure 23. Memory Self-Test / Initialization Control Register (MSIENA) Address

Strany 19 - 2.10 Clock Domains

Standard Initialization Sequence for Hercules Microcontrollerswww.ti.comThe Cortex-R4F CPU can operate in one of several modes:• User mode (USR) is th

Strany 20

Interrupt vector table address space0xFFF820000xFFF820040xFFF82008Phantom VectorChannel 0 VectorChannel 1 VectorChannel 93 VectorChannel 94 Vector0xFF

Strany 21 - Reserved PENA Reserved

Standard Initialization Sequence for Hercules Microcontrollerswww.ti.com2.21.1 Example VIM RAM Configurationtypedef void (*t_isrFuncPTR)();#define VIM

Strany 22 - 2.13 Memories’ Self-Test

www.ti.comStandard Initialization Sequence for Hercules MicrocontrollerserayT0CInterrupt, /* phantomInterrupt for RM4x */spi5HighLevelInterrupt,spi4Lo

Strany 23

3MFlashwithECC64K64K64K64K256KRAMwithECCETM-R4(CPU Trace)Dual Cortex-R4FCPUs in LockstepRTP(RAM Trace)DMAPOMDMMHTU1FTUHTU2EMACSwitched Centrol Resourc

Strany 24

Standard Initialization Sequence for Hercules Microcontrollerswww.ti.com2.21.2 Configure Interrupts to be Fast Interrupts or Normal InterruptsTwo regi

Strany 25 - DONE DONE

www.ti.comStandard Initialization Sequence for Hercules MicrocontrollersThe interrupt enable set register 1 (REQENASET1) is shown in Figure 29.Figure

Strany 26

Referenceswww.ti.comThe VIC port is disabled upon any CPU reset and must be enabled by the application. The VIC is enabledby setting the VE bit in the

Strany 27 - Cortex™-R4F Microcontrollers

IMPORTANT NOTICETexas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improveme

Strany 28

Standard Initialization Sequence for Hercules Microcontrollerswww.ti.com2 Standard Initialization Sequence for Hercules MicrocontrollersA basic sequen

Strany 29

OSCIN/NR/1 to /64INTCLKPLL/NF/1 to /256VCOCLK/OD/1 to /8post_ODCLK/R/1 to /32PLLCLKf = (f / NR) * NF / (OD * R)PLLCLK OSCINf = (f / NR2) * NF2 / (OD2

Strany 30

Standard Initialization Sequence for Hercules Microcontrollerswww.ti.comNOTE: The FMPLL takes (127 + 1024*NR) oscillator cycles to acquire lock to the

Strany 31

www.ti.comStandard Initialization Sequence for Hercules MicrocontrollersTable 1. PLL Control Register (PLLCTL1) Field Descriptions (continued)Bit Fiel

Strany 32 - 3 References

Standard Initialization Sequence for Hercules Microcontrollerswww.ti.com2.3 Enable Clock Sources2.3.1 Available Clock Sources on Hercules Microcontrol

Strany 33 - IMPORTANT NOTICE

www.ti.comStandard Initialization Sequence for Hercules MicrocontrollersThe clock source disable register (CSDISSET) is shown in Figure 7.Figure 7. Cl

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