ARM Cortex r1p3 Datový list Strana 71
- Strana / 138
- Tabulka s obsahem
- KNIHY
Hodnocené. / 5. Na základě hodnocení zákazníků
DocID024647 Rev 1 71/138
RM0352 I
2
C bus interface
137
10 I
2
C bus interface
The Brain device provides two I
2
C bus interfaces that support following features:
• Slave transmitter/receiver and master transmitter/receiver
• 7- and 10-bit addressing
• Standard (100 KHz) and fast (400 KHz) speeds
• The transmit path is buffered in a 16-byte Tx FIFO and the receive paths is buffered in
a 16-byte Rx FIFO.
In addition to receiving and transmitting data, the interface converts data from serial to
parallel format and vice-versa using an interrupt or polled handshake. The interrupts are
enabled and disabled in software.
10.1 I
2
C registers
The base address of the I
2
C blocks in Brain memory map is 0xA400_0000 for I2C1 and
0xA500_0000 for I2C2.
Table 70. I
2
C register list
(1)
Address Name Description
I
2
C Base +0x000 I2C_CR
I
2
C control register. See Section 10.2.1: I2C control register
(I2C_CR) on page 73.
I
2
C Base +0x004 I2C_SCR
I
2
C slave control register. See Section 10.2.2: I2C slave control
register (I2C_SCR) on page 77.
I
2
C Base +0x008 RESERVED This register must not be written and must keep its reset value
I
2
C Base +0x00C I2C_MCR
I
2
C master control register. See Section 10.2.3: I2C master
control register (I2C_MCR) on page 77.
I
2
C Base +0x010 I2C_TFR
I
2
C transmit FIFO register. See Section 10.2.4: I2C transmit FIFO
register (I2C_TFR) on page 79.
I
2
C Base +0x014 I2C_SR
I
2
C status register. See Section 10.2.5: I2C status register
(I2C_SR) on page 80.
I
2
C Base +0x018 I2C_RFR
I
2
C receive FIFO register. See Section 10.2.6: I2C receive FIFO
register (I2C_RFR) on page 83.
I
2
C Base +0x01C I2C_TFTR
I
2
C transmit FIFO threshold register. See Section 10.2.7: I2C
transmit FIFO threshold register (I2C_TFTR) on page 84.
I
2
C Base +0x020 I2C_RFTR
I
2
C receive FIFO threshold register. See Section 10.2.8: I2C
receive FIFO threshold register (I2C_RFTR) on page 84.
I
2
C Base +0x024 RESERVED This register must not be written and must keep its reset value
I
2
C Base +0x028 I2C_BRCR
I
2
C baud rate counter register. See Section 10.2.9: I2C baud-rate
counter register (I2C_BRCR) on page 85.
I
2
C Base +0x02C I2C_IMSCR
I
2
C interrupt mask set and clear register. See Section 10.2.10:
I2C interrupt mask set/clear register (I2C_IMSCR) on page 86.
I
2
C Base +0x030 I2C_RISR
I
2
C raw interrupt status register. See Section 10.2.11: I2C raw
interrupt status register (I2C_RISR) on page 88.
- Reference manual 1
- Contents 2
- DocID024647 Rev 1 3/138 3
- 4/138 DocID024647 Rev 1 4
- DocID024647 Rev 1 5/138 5
- 6/138 DocID024647 Rev 1 6
- List of tables 7
- 8/138 DocID024647 Rev 1 8
- DocID024647 Rev 1 9/138 9
- List of figures 10
- 1 Referenced document 11
- 2 System and memory overview 12
- 2.2 Memory organization 13
- 2.3 Embedded SRAM 15
- 2.4 Flash memory overview 15
- 2.5 Physical remap 16
- Interrupts RM0352 18
- Table 3. Interrupt vectors 18
- (continued) 18
- 5.1 Introduction 21
- 5.2 Clock generation 21
- Figure 2. Clock generation 22
- DocID024647 Rev 1 23/138 23
- 5.3 Reset generation 24
- 5.3.2 Power-on reset 25
- 5.3.3 ECC reset 25
- 5.3.4 Watchdog reset 25
- 5.3.5 System reset request 26
- 5.3.6 Lockup reset 26
- 5.3.7 Recall done 26
- 6.3.4 Command register 34
- MASS ERASE 34
- DocID024647 Rev 1 37/138 37
- 0-Unlocked 37
- 1NoLocked 37
- 1 Yes Unlocked 37
- Watchdog timer (WDG) RM0352 40
- Table 26. WDG register list 40
- dual timer module (SP804) 47
- 8.2 Functional overview 48
- DocID024647 Rev 1 49/138 49
- 8.2.2 Functional description 50
- Free running counter blocks 51
- Interface reset 51
- Prescaler operation 52
- Timer operation 53
- 54/138 DocID024647 Rev 1 54
- Interrupt behavior 55
- 56/138 DocID024647 Rev 1 56
- 8.3 Programmer's model 57
- 8.3.2 Register descriptions 59
- Load register, TimerXLoad 60
- ". 63
- 9.4 Configuring SysTick 70
- C bus interface RM0352 72
- Table 70. I 72
- C register list 72
- 74/138 DocID024647 Rev 1 74
- DocID024647 Rev 1 75/138 75
- 76/138 DocID024647 Rev 1 76
- 78/138 DocID024647 Rev 1 78
- 10.2.5 I 80
- C status register (I2C_SR) 80
- DocID024647 Rev 1 81/138 81
- 82/138 DocID024647 Rev 1 82
- DocID024647 Rev 1 87/138 87
- DocID024647 Rev 1 89/138 89
- 90/138 DocID024647 Rev 1 90
- DocID024647 Rev 1 91/138 91
- 11.1 Features 100
- 11.2 Clock prescaler 100
- 101
- 11.5.4 SSPRTINTR 114
- 11.5.1 SSPRXINTR 114
- 11.5.2 SSPTXINTR 114
- 11.5.3 SSPRORINTR 114
- 12.1 Features 115
- 12.2 IrDA SIR block 116
- 12.3 Baud rate generator 116
- 12.4 Interrupts 116
- 12.4.1 UARTMSINTR 117
- 12.4.2 UARTRXINTR 117
- 12.4.3 UARTTXINTR 117
- 12.5 UART registers 118
- 12.6 Register descriptions 120
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