ARM VERSION 1.2 Uživatelská příručka

ARM® Developer SuiteVersion 1.2Developer GuideARM Developer SuiteCopyright ?1999-2001 ARM Limited. All rights reserved.Change HistoryThe following cha

• be assembled with the -apcs options selected.2.1.4 Processes and the memory modelATPCS applies to a single thread of execution or process. The memo

000004 e3a00440 MOV r0,#0x40000000000008 e5801000 STR r1,[r0,#0];;;12 int_val = *PortLoad;00000c e5901000

Peripheral locations should not be accessed using __packed structs (where unaligned members are allowed andthere is no internal padding), or using C b

The benefits of using a scatter description file are:• All the (target-specific) absolute addresses chosen for your devices, code, and data are locate

6.10 TroubleshootingThis section provides solutions to the following common problems:• Linker error __semihosting_swi_guard• Setting $top_of_memory•

Retarget __user_initial_stackheap()__user_initial_stackheap() must be reimplemented if you are using scatter loading.Ensure that you have reimplemente

6.11 Measuring code and data sizeTo measure code size, do not look at the linked image size or object module size, as these include symbolicinformati

7 Caches and Tightly Coupled MemoriesThis chapter describes some aspects of initializing cached processors. It also describes processors with tightly

• use the Pagetable model throughout your development work, unless you are writing an operating system. Thisoption is recommended if you are writing a

7.2 System control coprocessorCP15 is the system control coprocessor. You must write to registers in CP15 to configure your core, and any cachesor TC

7.3 Memory protection unitsProtection Units (PUs) partition memory into regions. For each region you can specify:SizeTypically this might range from

2.2 Register roles and namesThe ATPCS specifies the registers to use for particular purposes.2.2.1 Register rolesThe following register usage applie

7.4 Configuring a PUTo configure a PU, you must do the following:1. Define the starting addresses and sizes of protection regions, and enable them.

• When you load from that region, the cache is searched. If the item is found, it is loaded from the cache. If theitem is not found, a complete cache

7.4.4 Configuring core operationCoprocessor register c1 of CP15 is the core configuration register. You must use a read-modify-write cycle to alterth

7.5 Memory management unitsMemory Management Units (MMUs):• translate virtual addresses into physical addresses• control memory access permissions.If

7.5.2 Memory access permissions and domainsTranslation tables also hold access permission fields and a domain field.There are 16 domains, Each region

7.6 Configuring an MMUTo configure an MMU, you must do the following:1. Build the translation table in memory. Translation tables include:• virtual

LDR r1,=0x0 ; Read first entry in translation table, which points to a 1MB section at 0x0 LDR r2,[r0,r1,LSL#2] ORR r2,r2,#2_1000

7.7 Tightly coupled memoryUse normal memory access instructions to access TCM. The address is the only difference between an instruction toaccess TCM

• use literal pools• set software breakpoints for debugging• download code• write self-modifying code.Instruction fetches from data TCM are not allowe

• For one cycle, when a read from data TCM immediately follows a write to data TCM.• For one cycle, when a data read from instruction TCM occurs.• For

2.3 The stackThis section describes how to use the stack in the base standard. See also Stack limit checking.ATPCS specifies:• a full, descending sta

8 Debug Communications ChannelThis chapter explains how to use of the Debug Communications Channel (DCC). It contains the following sections:• About

8.2 Command-line debugging commandsTo access the debug communications channel from a command line using armsd use the following commands:ccin filenam

8.3 Enabling comms channel viewingDebug communications channel viewing is supported in AXD.8.3.1 Comms channel viewing in AXDTo enable channel viewi

8.4 Target transfer of dataThe debug communications channel is accessed by the target as coprocessor 14 on the ARM core using the ARMinstructions MCR

8.5 Polled debug communicationsIn addition to the comms data read and write registers, a comms data control register is provided by the debugcommunic

; into r3 and update the pointer MCR p14,0,r3,c1,c0 ; Write word from r3 SUBS r1,r1,#1 ; Update counter

The following piece of target application code, supplied in fileInstall_directory\Examples\dcc\inchan.s, shows this in action: AREA InChannel, CO

If you view the area of memory indata, you see its initial contents:examine indata5. In the AXD main screen, select Go from the Execute menu (or pres

8.6 Interrupt-driven debug communicationsThe examples given above demonstrate polling the DCC. You can convert these to interrupt-driven examples byc

8.7 Access from Thumb stateBecause the Thumb instruction set does not contain coprocessor instructions, you cannot use the debugcommunications channe

To comply with the ATPCS in assembly language, unless your object file contains no external calls, you must:• Ensure that 8-byte alignment of the stac

8.8 SemihostingYou can use the debug communications channel for semihosting if you are using Multi-ICE with$semihosting_enabled=2. See the Multi-ICE

GlossaryADSSee ARM Developer Suite.ANSIAmerican National Standards Institute. An organization that specifiesstandards for, among other things, compute

InterworkingProducing an application that uses both ARM and Thumb code.LibraryA collection of assembler or compiler output objects grouped together in

processor and may or may not be associated with an image.VeneerA small block of code used with subroutine calls when there is a requirementto change p

2.4 Parameter passingA routine with a variable number of arguments is variadic. A routine with a fixed number of arguments is nonvariadic.There are d

2.5 Stack limit checkingSelect the software stack limit checking (/swst) option unless the maximum amount of stack memory required byyour complete pr

NoteThe names __ARM_stack_overflow and __Thumb_stack_overflow are illustrative and do not correspond toany actual implementation.Routine using more th

2.6 Read-only position independenceA program is Read-Only Position-Independent (ROPI) if all its read-only segments are position independent.An ROPI

2.7 Read-write position independenceA program is Read-Write Position-Independent (RWPI) if all its read-write segments are position independent.An RW

2.8 Interworking between ARM and Thumb statesSelect the /interwork option when compiling or assembling code if you want:• ARM routines to be able to

PrefaceThis preface introduces the ARM Developer Suite (ADS) Developer Guide. It contains the following sections:• About this book• Feedback.About thi

2.9 Floating-point optionsThe ATPCS supports two different floating-point hardware architectures and instruction sets:• The VFP architecture (see The

Format of VFP valuesSingle-precision and double-precision values conform to the IEEE 754 standard formats. Double-precision values aretreated as true

3 Interworking ARM and ThumbThis chapter explains how to change between ARM state and Thumb state when writing code for processors thatimplement the

• Thumb subroutines that might make indirect or virtual calls to ARM code• ARM subroutines that might make indirect or virtual calls to Thumb code.Oth

3.2 Assembly language interworkingIn an assembly language source file, you can have several areas (these correspond to ELF sections). Each area canco

• A BX instruction to branch to the Thumb code and change processor state.The second section of the module, labelled ThumbProg, is prefixed by a CODE1

• If LDR, LDM, or POP load to the pc, they set the Thumb bit in the CPSR to bit[0] of the value loaded to the pc.You can use this to change instructio

3.3 C and C++ interworking and veneersYou can freely mix C and C++ code compiled for ARM and Thumb, but in ARM architecture v4T small codesegments ca

To compile and link these modules:1. Type tcc -c -apcs /interwork -o thumbmain.o thumbmain.c at the system prompt to compile theThumb code for interwo

3.4 Assembly language interworking using veneersThe assembly language ARM/Thumb interworking method described in Assembly language interworking carri

developing code for the ARM family of processors.ARM periodically provides updates and corrections to its documentation. See http://www.arm.com for cu

armsd: list 0x8000ARMProg 0x00008000: 0xe3a00001 ... : > mov r0,#1 0x00008004: 0xeb000005 ... : bl $Ven$AT$$ThumbProg

4. Type armsd add to load the code.5. Type go to run the code.6. Type list main to list the code generated for the main function.7. Type list arm_func

4 Mixing C, C++, and Assembly LanguageThis chapter describes how to write mixed C, C++, and ARM assembly language code. It also describes how to uset

String copying exampleExample 4-1 shows how to use labels and branches in a string copy routine.This code is also in install_directory\examples\inline

NoteUsing physical register names is not recommended, because it constrains compiler register allocation and can causeless efficient code to be genera

• The LDR Rn, =expression pseudo-instruction is not supported. Use MOV Rn, expression instead (thiscan generate a load from a literal pool).• Label ex

{ MOV ip, #3 ADDS x, x, #0x12345678 // this instruction is expanded ORR x, x, ip }The compiler uses ip as a temporary register when it expands

int tmp; __asm { MRS tmp, CPSR ORR tmp, tmp, #0x80 MSR CPSR_c, tmp }}int main(void){ disable_IRQ(); enable_IRQ

Writing the multiply routine in C:// long multiply routine in Clong long smull(int x, int y){ return (long long) x * (long long) y;}The compiler ge

4.2 Accessing C global variables from assembly codeGlobal variables can only be accessed indirectly, through their address. To access a global variab

FeedbackARM Limited welcomes feedback on both the ARM Developer Suite, and its documentation.Feedback on the ARM Developer SuiteIf you have any proble

4.3 Using C header files from C++This section describes how to use C header files from your C++ code. C header files must be wrapped in extern"C

} /* The C header file can now be */#endif /* included in either C or C++ code. */Mixing C, C++, and Assembly LanguageC

4.4 Calling between C, C++, and ARM assembly languageThis section provides examples that can help you to call C and assembly language code from C++,

they have no base classes or virtual functions. If such a struct has neither a user-defined copy assignmentoperator or a user-defined destructor, it i

2. Type armcc -c -g strtest.c to build the C source.3. Type armlink strtest.o scopy.o -o strtest to link the object files4. Type armsd -e strtest exec

int f() { S s(2); // initialize 's' asmfunc(&s); // call 'asmfunc' so it

f STMFD sp!,{lr} MOV r0,#2 STR r0,[sp,#-4]! ; initialize struct MOV r0,sp ; argument is pointer to struct BL cppfu

/* Definition of the C function to be called from C++. */ return 3 * f__1TFi(t, 2); /* like '3 * t->f(2)' */}Example 4-25 Implemen

5 Handling Processor ExceptionsThis chapter describes how to handle the various types of exception supported by ARM processors. It contains thefollow

5.1.1 The vector tableProcessor exception handling is controlled by a vector table. The vector table is a reserved area of 32 bytes, usuallyat the bo

1 IntroductionThis chapter introduces the ADS Developer Guide. It contains the following sections:• About the ARM Developer Guide• General programing

5.2 Entering and leaving an exceptionThis section describes the processor response to an exception, and how to return to the place where an exception

Returning from SWI and Undefined Instruction handlersThe SWI and Undefined Instruction exceptions are generated by the instruction itself, so the prog

5.3 Installing an exception handlerAny new exception handler must be installed in the vector table. When installation is complete, the new handlerexe

Sometimes during development work it is necessary to install exception handlers into the vectors directly from themain application. As a result, the r

/* instruction to cause long branch to address in `location'. *//* Function return value is original contents of 'vector'. */{ unsign

5.4 SWI handlersWhen the SWI handler is entered, it must establish which SWI is being called. This information can be stored in bits0-23 of the instr

5.4.2 SWI handlers in C and assembly languageAlthough the top-level handler must always be written in ARM assembly language, the routines that handle

Figure 5-2 Accessing the supervisor stack5.4.3 Using SWIs in Supervisor modeWhen a SWI instruction is executed:1. The processor enters Supervisor mo

From C/C++, declare the SWI as an __SWI function, and call it. For example: __swi(0) void my_swi(int); . . . my_swi(65);This allows a S

occur, for example, when there are a number of related operations that can be performed on an object, and eachoperation has its own SWI. In such a cas

1.2 General programing issuesThe ARM family of processors are RISC processors. Many of the programing strategies that give efficient code aregeneric

__swi (0) char __ReadCharacter (unsigned op);__swi (0) void __WriteCharacter (unsigned op, char c);These can be used in a more reader-friendly fashion

5.5 Interrupt handlersThe ARM processor has two levels of external interrupt, FIQ and IRQ, both of which are level-sensitive active LOWsignals into t

MOV r4,#0x80000000 LDR r0,[r4,#0] SUB sp,sp,#4 CMP r0,#1 BLEQ C_int_handler MOV

; Add instructions to clear the interrupt here ; then re-enable interrupts. MSR CPSR_c, #0x1F ; switch to SYS mode, FIQ and IRQ

IOPort1,IOPort2Are offsets to the two data registers to be read. Reading a data register clears theinterrupt for the corresponding port.r9Points to th

; PC base address points to this ; instruction + 8 NOP

MSRNE SPSR_cxsf, r0 ; Restore the status. LDMNEIA r13, {r0 - r14}^ ; Get the rest of the registers NOP SUBNES pc, lr,

5.6 Reset handlersThe operations carried out by the Reset handler depend on the system for which the software is being developed.For example, it may:

5.7 Undefined Instruction handlersInstructions that are not recognized by the processor are offered to any coprocessors attached to the system. If th

5.8 Prefetch Abort handlerIf the system has no MMU, the Prefetch Abort handler can simply report the error and quit. Otherwise the addressthat caused

1.3 Developing for the ARMThis book gives information and example code for some of the most common ARM programing tasks. The followingsections summar

5.9 Data Abort handlerIf there is no MMU, the Data Abort handler should simply report the error and quit. If there is an MMU, the handlershould deal

5.10 Chaining exception handlersIn some situations there can be several different sources of a particular exception. For example:• Angel uses an Unde

5.11 Handling exceptions on Thumb-capable processorsThis section describes the additional considerations you must take into account when writing exce

The following sections give a summary of the values to which the processor sets lr_mode if an exception occurswhen the processor is in Thumb state.SWI

; r0 now contains SWI number CMP r0, #MaxSWI ; Rangecheck LDRLS pc, [pc, r0, LSL#2] ; Jump to the appr

5.12 System modeThe ARM Architecture defines a User mode that has 15 general purpose registers, a pc, and a CPSR. In addition tothis mode there are f

6 Writing Code for ROMThis chapter describes how to build images for embedded applications. These images are typically programmed intoROM or flash me

6.2 Memory map considerationsA major consideration in the design of an embedded ARM application is the layout of the memory map, in particularthe mem

2. Execute the RESET vector:LDR PC, =0x0F000004This causes a jump to the real address of the next ROM instruction. This assembles to a position-indep

6.3 Initializing the systemThere are two initialization stages:1. Initializing the execution environment, for example exception vectors, stacks, I/O

Data AbortOccurs when a data transfer instruction attempts to load or store data at an illegal address.Interrupt (IRQ)Occurs when the processor extern

See the code in the Examples\embedded\cache directory for examples of cache initialization code.Initializing the stack pointersThe initialization code

6.4 The reference C example using semihostingThis example shows an application that uses the semihosting SWIs. printf() is compiled as a call to a C

By default, the stack pointer sp is initialized to 0x08000000 for ARMulator. If you are using a development board,you must set $top_of_memory. For exa

6.5 Loading the ROM image at address 0Scatter loading provides a flexible mechanism for mapping code and data onto your memory map. These options are

vectors.o (Vect, +First) * (+RO) } RAM 0x28000000 { * (+RW,+ZI) } HEAP +0 UNINIT { heap.o (+ZI) }

ENDThe code in Example 6-4 performs ROM/RAM remapping (if required), initializes stack pointers and interrupts foreach mode, and finally branches

EXPORT Reset_HandlerReset_Handler; --- Initialize stack pointer registers; Enter each mode in turn and set up the stack pointer IMPORT

**** #define USE_SERIAL_PORT**** or compile with **** -DUSE_SERIAL_PORT*/ #include <stdio.h> #include <rt_misc.h> #ifdef __thum

config.stack_base = SP; // inherit sp from the execution environment return config;}/*Below is an equivalent example assembler version of __u

• a project file for the CodeWarrior IDE• a batch file• the command line.Using the CodeWarrior IDETo build the example from the CodeWarrior IDE, load

2 Using the Procedure Call StandardThis chapter describes how to use the ARM-Thumb Procedure Call Standard (ATPCS). Adhere to the ATPCS toensure that

6.6 Using both scatter loading and remappingThis section describes how to convert the application in Loading the ROM image at address 0 into a more c

HEAP +0 UNINIT ; The heap is not zero-initialized. ; The +0 specification means that the heap {

armasm -g vectors.sarmasm -g -PD "ROM_RAM_REMAP SETL {TRUE}" init.sarmasm -g stack.sarmasm -g heap.sREM Use the following two lines to build

6.7 A semihosted application with interrupt handlingThis section illustrates an Reference Peripheral Specification (RPS) based interrupt-driven timer

return (oldvec);} #endif/* Enabling and disabling interrupts Interrupts are enabled or disabled by reading the cpsr flags and updating bit 7.

*Timer2Load = MED_FAST_LOAD; *Timer1Control = (TimerEnable | // Enable the Timer TimerPeriodic | // Period

{ *Timer2Clear = 0;/* clear the interrupt */ IntCT2++; /* set the flag */ } }Writing Code for ROMCopyright ?1999 2001 ARM Limit

6.8 An embeddable application with interrupt handlingThis section describes how to convert the application in A semihosted application with interrupt

REM -DUSE_SERIAL_PORTREM armcc -c -g -O1 retarget.c -DUSE_SERIAL_PORTarmcc -c -g -O1 uart.c -I..\includearmcc -c -g -O1 serial.c -I..\

6.9 Using scatter loading with memory-mapped I/OIn most ARM embedded systems, peripherals are located at specific addresses in memory. You often need